From f8c738577f813bbe6cb017cfbb29b70582ab32b4 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 16 Sep 2024 23:12:18 +0200 Subject: [PATCH] UefiCpuPkg: RiscV64: initialize FPU The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt --- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 6 +++++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 1 + UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h | 21 +++++++++++++++ .../BaseRiscVFpuLib/BaseRiscVFpuLib.inf | 26 +++++++++++++++++++ .../Library/BaseRiscVFpuLib/RiscVFpuCore.S | 22 ++++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 2 ++ UefiCpuPkg/UefiCpuPkg.dsc | 1 + 8 files changed, 80 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index c6bae100a9..6a22e01711 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -359,6 +359,12 @@ InitializeCpu ( Status = RiscVConfigureMmu (); ASSERT_EFI_ERROR (Status); + // + // Initialize FPU + // + Status = RiscVInitializeFpu (); + ASSERT_EFI_ERROR (Status); + // // Install Boot protocol // diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index d4d67778eb..40077d65bd 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf index 9d9a5ef8f2..cb0f71e42e 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf @@ -38,6 +38,7 @@ PeCoffGetEntryPointLib RiscVSbiLib RiscVMmuLib + RiscVFpuLib CacheMaintenanceLib [Sources] diff --git a/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h b/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h new file mode 100644 index 0000000000..d75320ff74 --- /dev/null +++ b/UefiCpuPkg/Include/Library/BaseRiscVFpuLib.h @@ -0,0 +1,21 @@ +/** @file + + Copyright (c) 2024, Canonical Services Ltd
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef BASE_RISCV_FPU_LIB_H_ +#define BASE_RISCV_FPU_LIB_H_ + +/** + Initialize floating point unit + +**/ +EFI_STATUS +EFIAPI +RiscVInitializeFpu ( + VOID + ); + +#endif /* BASE_RISCV_FPU_LIB_H_ */ diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf new file mode 100644 index 0000000000..8130430310 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf @@ -0,0 +1,26 @@ +## @file +# RISC-V FPU library. +# +# Copyright (c) 2024, Canonical Services Ltd +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001b + BASE_NAME = BaseRiscVFpuLib + FILE_GUID = e600fe4d-8595-40f3-90a0-5f043ce155c2 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RiscVFpuLib + +[Sources] + RiscVFpuCore.S + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S new file mode 100644 index 0000000000..b439af4e42 --- /dev/null +++ b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S @@ -0,0 +1,22 @@ +/** @file +* +* Copyright (c) 2024, Canonical Services Ltd +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include + +// +// Initialize floating point unit +// +ASM_FUNC (RiscVInitializeFpu) + csrr a0, CSR_SSTATUS + li a1, MSTATUS_FS + or a0, a0, a1 + csrw CSR_SSTATUS, a0 + csrw CSR_FCSR, x0 + li a0, 0 + ret diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 33ac8cf91c..4e71a11ae0 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -75,6 +75,8 @@ SmmRelocationLib|Include/Library/SmmRelocationLib.h [LibraryClasses.RISCV64] + ## @libraryclass Provides function to initialize the FPU. + RiscVFpuLib|Include/Library/BaseRiscVFpuLib.h ## @libraryclass Provides functions to manage MMU features on RISCV64 CPUs. ## RiscVMmuLib|Include/Library/BaseRiscVMmuLib.h diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f173bba87e..d7f8e422d4 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -224,6 +224,7 @@ [Components.RISCV64] UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf + UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf