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ArmPlatformPkg/LcdGraphicsOutputDxe: Added support for ARM HDLCD controller (2)
... Forgot the new files git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13053 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
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125
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
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125
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
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/** @file Lcd.c
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/HdLcd.h>
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#include "LcdGraphicsOutputDxe.h"
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/**********************************************************************
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*
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* This file contains all the bits of the Lcd that are
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* platform independent.
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*
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**********************************************************************/
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EFI_STATUS
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LcdInitialize (
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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)
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{
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// Disable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
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// Disable all interrupts
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MmioWrite32(HDLCD_REG_INT_MASK, 0);
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// Define start of the VRAM. This never changes for any graphics mode
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MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);
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// Setup various registers that never change
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MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8);
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MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);
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MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);
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MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0));
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MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8));
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MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16));
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return EFI_SUCCESS;
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}
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EFI_STATUS
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LcdSetMode (
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IN UINT32 ModeNumber
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)
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{
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EFI_STATUS Status;
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UINT32 HRes;
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UINT32 HSync;
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UINT32 HBackPorch;
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UINT32 HFrontPorch;
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UINT32 VRes;
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UINT32 VSync;
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UINT32 VBackPorch;
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UINT32 VFrontPorch;
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UINT32 BytesPerPixel;
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LCD_BPP LcdBpp;
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// Set the video mode timings and other relevant information
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Status = LcdPlatformGetTimings (ModeNumber,
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&HRes,&HSync,&HBackPorch,&HFrontPorch,
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&VRes,&VSync,&VBackPorch,&VFrontPorch);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR( Status )) {
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return EFI_DEVICE_ERROR;
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}
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Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);
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ASSERT_EFI_ERROR (Status);
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if (EFI_ERROR( Status )) {
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return EFI_DEVICE_ERROR;
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}
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BytesPerPixel = GetBytesPerPixel(LcdBpp);
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// Disable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);
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// Update the frame buffer information with the new settings
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MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);
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MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel);
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MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1);
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// Set the vertical timing information
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MmioWrite32(HDLCD_REG_V_SYNC, VSync);
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MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch);
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MmioWrite32(HDLCD_REG_V_DATA, VRes - 1);
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MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch);
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// Set the horizontal timing information
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MmioWrite32(HDLCD_REG_H_SYNC, HSync);
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MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch);
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MmioWrite32(HDLCD_REG_H_DATA, HRes - 1);
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MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch);
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// Enable the controller
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MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);
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return EFI_SUCCESS;
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}
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VOID
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LcdShutdown (
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VOID
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)
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{
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// Nothing to do in terms of hardware.
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// We could switch off the monitor display if required
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}
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@ -0,0 +1,60 @@
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#/** @file
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#
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# Component description file for HDLCD module
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#
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# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = HdLcdGraphicsDxe
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FILE_GUID = ce660500-824d-11e0-ac72-0002a5d5c51b
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = LcdGraphicsOutputDxeInitialize
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[Sources.common]
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LcdGraphicsOutputDxe.c
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LcdGraphicsOutputBlt.c
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HdLcd.c
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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UefiLib
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BaseLib
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DebugLib
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TimerLib
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UefiDriverEntryPoint
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UefiBootServicesTableLib
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IoLib
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BaseMemoryLib
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LcdPlatformLib
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[Protocols]
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gEfiDevicePathProtocolGuid
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gEfiGraphicsOutputProtocolGuid # Produced
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gEfiEdidDiscoveredProtocolGuid # Produced
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gEfiEdidActiveProtocolGuid # Produced
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gEfiEdidOverrideProtocolGuid # Produced
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[FixedPcd]
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gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase
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[Depex]
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gEfiCpuArchProtocolGuid
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89
ArmPlatformPkg/Include/Drivers/HdLcd.h
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89
ArmPlatformPkg/Include/Drivers/HdLcd.h
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@ -0,0 +1,89 @@
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/** @file HDLcd.h
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _HDLCD_H_
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#define _HDLCD_H_
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//
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// HDLCD Controller Register Offsets
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//
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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//
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// HDLCD Values of registers
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//
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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// CLCD_CONTROL Control register
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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// Bus Options
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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// Polarities - HIGH
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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// Polarities - LOW (for completion and for ease of understanding the hardware settings)
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#endif /* _HDLCD_H_ */
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