Add runtime registration functions to the 4 PCI Library classes

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6703 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney 2008-11-24 08:29:02 +00:00
parent ab95d5f223
commit f926e538ce
4 changed files with 96 additions and 0 deletions

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@ -39,6 +39,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
/**
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@retval RETURN_UNSUPPORTED An attempt was made to call this function
after ExitBootServices().
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
at runtime could not be mapped.
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
complete the registration.
**/
RETURN_STATUS
EFIAPI
PciCf8RegisterForRuntimeAccess (
IN UINTN Address
);
/**
Reads an 8-bit PCI configuration register.

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@ -38,6 +38,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
/**
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@retval RETURN_UNSUPPORTED An attempt was made to call this function
after ExitBootServices().
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
at runtime could not be mapped.
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
complete the registration.
**/
RETURN_STATUS
EFIAPI
PciExpressRegisterForRuntimeAccess (
IN UINTN Address
);
/**
Reads an 8-bit PCI configuration register.

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@ -40,6 +40,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
/**
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@retval RETURN_UNSUPPORTED An attempt was made to call this function
after ExitBootServices().
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
at runtime could not be mapped.
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
complete the registration.
**/
RETURN_STATUS
EFIAPI
PciRegisterForRuntimeAccess (
IN UINTN Address
);
/**
Reads an 8-bit PCI configuration register.

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@ -63,6 +63,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
(LShiftU64((Segment) & 0xffff, 32)) \
)
/**
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@retval RETURN_UNSUPPORTED An attempt was made to call this function
after ExitBootServices().
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
at runtime could not be mapped.
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
complete the registration.
**/
RETURN_STATUS
EFIAPI
PciSegmentRegisterForRuntimeAccess (
IN UINTN Address
);
/**
Reads an 8-bit PCI configuration register.