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MdeModulePkg/PciHostBridgeDxe: Fix a Base/Limit comparing bug 

When the aperture base equals to aperture limit, the old code treats
the aperture as non-existent. It's not correct because it indicates
a range starting with base and the length is 1.
The new code corrects the comparing bug.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Ruiyu Ni 2016-04-29 17:38:51 +08:00
parent 814f4306d8
commit f9607bef04
2 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c
View File

@ -393,7 +393,7 @@ InitializePciHostBridge (
continue;
}
if (RootBridges[Index].Io.Limit > RootBridges[Index].Io.Base) {
if (RootBridges[Index].Io.Base <= RootBridges[Index].Io.Limit) {
Status = AddIoSpace (
RootBridges[Index].Io.Base,
RootBridges[Index].Io.Limit - RootBridges[Index].Io.Base + 1
@ -413,7 +413,7 @@ InitializePciHostBridge (
MemApertures[3] = &RootBridges[Index].PMemAbove4G;
for (MemApertureIndex = 0; MemApertureIndex < sizeof (MemApertures) / sizeof (MemApertures[0]); MemApertureIndex++) {
if (MemApertures[MemApertureIndex]->Limit > MemApertures[MemApertureIndex]->Base) {
if (MemApertures[MemApertureIndex]->Base <= MemApertures[MemApertureIndex]->Limit) {
Status = AddMemoryMappedIoSpace (
MemApertures[MemApertureIndex]->Base,
MemApertures[MemApertureIndex]->Limit - MemApertures[MemApertureIndex]->Base + 1,

24
MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
View File

@ -95,25 +95,25 @@ CreateRootBridge (
//
// Make sure Mem and MemAbove4G apertures are valid
//
if (Bridge->Mem.Base < Bridge->Mem.Limit) {
if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
ASSERT (Bridge->Mem.Limit < SIZE_4GB);
if (Bridge->Mem.Limit >= SIZE_4GB) {
return NULL;
}
}
if (Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) {
if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
}
}
if (Bridge->PMem.Base < Bridge->PMem.Limit) {
if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
ASSERT (Bridge->PMem.Limit < SIZE_4GB);
if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
}
}
if (Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit) {
if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
return NULL;
@ -126,10 +126,10 @@ CreateRootBridge (
// support separate windows for Non-prefetchable and Prefetchable
// memory.
//
ASSERT (Bridge->PMem.Base >= Bridge->PMem.Limit);
ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);
if ((Bridge->PMem.Base < Bridge->PMem.Limit) ||
(Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)
ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
(Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
) {
return NULL;
}
@ -140,10 +140,10 @@ CreateRootBridge (
// If this bit is not set, then the PCI Root Bridge does not support
// 64 bit memory windows.
//
ASSERT (Bridge->MemAbove4G.Base >= Bridge->MemAbove4G.Limit);
ASSERT (Bridge->PMemAbove4G.Base >= Bridge->PMemAbove4G.Limit);
if ((Bridge->MemAbove4G.Base < Bridge->MemAbove4G.Limit) ||
(Bridge->PMemAbove4G.Base < Bridge->PMemAbove4G.Limit)
ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
(Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
) {
return NULL;
}