diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 3c3df6d983..f660e65aac 100644
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -108,6 +108,7 @@
 #define TCR_PS_256TB                            (5 << 16)
 
 #define TCR_TG0_4KB                             (0 << 14)
+#define TCR_TG1_4KB                             (2 << 30)
 
 #define TCR_IPS_4GB                             (0ULL << 32)
 #define TCR_IPS_64GB                            (1ULL << 32)
@@ -116,6 +117,7 @@
 #define TCR_IPS_16TB                            (4ULL << 32)
 #define TCR_IPS_256TB                           (5ULL << 32)
 
+#define TCR_EPD1                                (1 << 23)
 
 #define TTBR_ASID_FIELD                      (48)
 #define TTBR_ASID_MASK                       (0xFF << TTBR_ASID_FIELD)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 377a7858d4..f967a64788 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -628,7 +628,8 @@ ArmConfigureMmu (
       return RETURN_UNSUPPORTED;
     }
   } else if (ArmReadCurrentEL () == AARCH64_EL1) {
-    TCR = T0SZ | TCR_TG0_4KB;
+    // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
+    TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
 
     // Set the Physical Address Size using MaxAddress
     if (MaxAddress < SIZE_4GB) {