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Add code to protect the whole BIOS region on SPI flash, except UEFI Variable region.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17618 6f19259b-4bc3-4df7-8a09-765794883524
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@ -353,12 +353,23 @@ SpiBiosProtectionFunction(
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{
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{
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UINTN mPciD31F0RegBase;
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UINTN mPciD31F0RegBase;
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UINTN BiosFlaLower = 0;
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UINTN BiosFlaLower0;
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UINTN BiosFlaLimit = 0x7fffff;
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UINTN BiosFlaLimit0;
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UINTN BiosFlaLower1;
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BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
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UINTN BiosFlaLimit1;
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BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
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BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
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#ifdef MINNOW2_FSP_BUILD
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BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);
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BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
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#else
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BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
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BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
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#endif
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mPciD31F0RegBase = MmPciAddress (0,
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mPciD31F0RegBase = MmPciAddress (0,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_DEVICE_NUMBER_PCH_LPC,
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@ -391,7 +402,7 @@ SpiBiosProtectionFunction(
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//
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//
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MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
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MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
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B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
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B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
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(B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));
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(B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
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//
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//
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//Lock down PR0
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//Lock down PR0
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@ -405,6 +416,25 @@ SpiBiosProtectionFunction(
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DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
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DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
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}
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}
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//
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//Set PR1
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//
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MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
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B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
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(B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
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//
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//Lock down PR1
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//
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MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
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//
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// Verify if it's really locked.
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//
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if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
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DEBUG((EFI_D_ERROR, "Failed to lock down PR1.\n"));
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}
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return;
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return;
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}
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}
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@ -690,7 +720,7 @@ InitializePlatform (
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&mReadyToBootEvent
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&mReadyToBootEvent
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);
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);
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//
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//
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// Create a ReadyToBoot Event to run enable PR0 and lock down
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// Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
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//
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//
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if(mSystemConfiguration.SpiRwProtect==1) {
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if(mSystemConfiguration.SpiRwProtect==1) {
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Status = EfiCreateEventReadyToBootEx (
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Status = EfiCreateEventReadyToBootEx (
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@ -62,6 +62,7 @@
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Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
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Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
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SecurityPkg/SecurityPkg.dec
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SecurityPkg/SecurityPkg.dec
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CryptoPkg/CryptoPkg.dec
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CryptoPkg/CryptoPkg.dec
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IntelFspWrapperPkg/IntelFspWrapperPkg.dec
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[LibraryClasses]
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[LibraryClasses]
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BaseLib
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BaseLib
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@ -133,7 +134,13 @@
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
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gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
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gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress
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gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress
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gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress
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gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection
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gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
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gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase
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gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase
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[Depex]
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[Depex]
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gEfiPciRootBridgeIoProtocolGuid AND
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gEfiPciRootBridgeIoProtocolGuid AND
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