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ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled 

Some platforms may set up a preliminary ID map in flash and enter EFI
with the MMU and caches enabled, as this removes a lot of the complexity
around cache coherency. Let's take this into account, and avoid touching
the MMU controls or perform cache invalidation when the MMU is enabled
at entry.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
This commit is contained in:
Ard Biesheuvel 2022-07-01 20:24:26 +02:00 committed by mergify[bot]
parent b28acb22e0
commit fb493ac84e
1 changed files with 12 additions and 10 deletions
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22
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
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@ -58,17 +58,19 @@ CEntryPoint (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
) )
{ {
// Data Cache enabled on Primary core when MMU is enabled. if (!ArmMmuEnabled ()) {
ArmDisableDataCache (); // Data Cache enabled on Primary core when MMU is enabled.
// Invalidate instruction cache ArmDisableDataCache ();
ArmInvalidateInstructionCache (); // Invalidate instruction cache
// Enable Instruction Caches on all cores. ArmInvalidateInstructionCache ();
ArmEnableInstructionCache (); // Enable Instruction Caches on all cores.
ArmEnableInstructionCache ();
InvalidateDataCacheRange ( InvalidateDataCacheRange (
(VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
PcdGet32 (PcdCPUCorePrimaryStackSize) PcdGet32 (PcdCPUCorePrimaryStackSize)
); );
}
// //
// Note: Doesn't have to Enable CPU interface in non-secure world, // Note: Doesn't have to Enable CPU interface in non-secure world,