ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled

Some platforms may set up a preliminary ID map in flash and enter EFI
with the MMU and caches enabled, as this removes a lot of the complexity
around cache coherency. Let's take this into account, and avoid touching
the MMU controls or perform cache invalidation when the MMU is enabled
at entry.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

ArmPlatformPkg/PrePeiCore/PrePeiCore.c

@@ -58,6 +58,7 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint
   )
 {
+  if (!ArmMmuEnabled ()) {
     // Data Cache enabled on Primary core when MMU is enabled.
     ArmDisableDataCache ();
     // Invalidate instruction cache
@@ -69,6 +70,7 @@ CEntryPoint (
       (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
       PcdGet32 (PcdCPUCorePrimaryStackSize)
       );
+  }
 
   //
   // Note: Doesn't have to Enable CPU interface in non-secure world,