mirror of https://github.com/acidanthera/audk.git
ArmPkg/CpuPei: Get the System Memory from the Resource Memory HOB
Declare the system memory provided by the first Resource Memory HOB as cached memory to the MMU. All the remaining memory space is declared as Device Memory. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11861 6f19259b-4bc3-4df7-8a09-765794883524
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/**@file
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/**@file
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Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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which accompanies this distribution. The full text of the license may be found at
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@ -45,11 +46,40 @@ Abstract:
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
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VOID
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EFI_STATUS
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JamArmMmuConfig ( VOID )
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FindMainMemory(
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OUT UINT32 *PhysicalBase,
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OUT UINT32 *Length
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)
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{
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{
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EFI_PEI_HOB_POINTERS NextHob;
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// look at the resource descriptor hobs, choose the first system memory one
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NextHob.Raw = GetHobList ();
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while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
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if(NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)
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{
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*PhysicalBase = (UINT32)NextHob.ResourceDescriptor->PhysicalStart;
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*Length = (UINT32)NextHob.ResourceDescriptor->ResourceLength;
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return EFI_SUCCESS;
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}
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NextHob.Raw = GET_NEXT_HOB (NextHob);
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}
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return EFI_NOT_FOUND;
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}
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VOID
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ConfigureMmu ( VOID )
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{
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EFI_STATUS Status;
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UINTN Idx;
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UINT32 CacheAttributes;
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UINT32 CacheAttributes;
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ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[3];
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UINT32 SystemMemoryBase;
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UINT32 SystemMemoryLength;
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UINT32 SystemMemoryLastAddress;
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ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[4];
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VOID *TranslationTableBase;
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VOID *TranslationTableBase;
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UINTN TranslationTableSize;
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UINTN TranslationTableSize;
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@ -59,24 +89,48 @@ JamArmMmuConfig ( VOID )
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
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}
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}
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// DDR
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Idx = 0;
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MemoryTable[0].PhysicalBase = 0;
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MemoryTable[0].VirtualBase = 0;
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// Main Memory
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MemoryTable[0].Length = 0x10000000;
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Status = FindMainMemory (&SystemMemoryBase, &SystemMemoryLength);
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MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
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ASSERT_EFI_ERROR (Status);
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// SOC Registers. L3 interconnects
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SystemMemoryLastAddress = SystemMemoryBase + (SystemMemoryLength-1);
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MemoryTable[1].PhysicalBase = 0x10000000;
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MemoryTable[1].VirtualBase = 0x10000000;
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// if system memory does not begin at 0
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MemoryTable[1].Length = 0xF0000000;
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if(SystemMemoryBase > 0) {
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MemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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MemoryTable[Idx].PhysicalBase = 0;
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MemoryTable[Idx].VirtualBase = 0;
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MemoryTable[Idx].Length = SystemMemoryBase;
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MemoryTable[Idx].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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Idx++;
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}
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MemoryTable[Idx].PhysicalBase = SystemMemoryBase;
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MemoryTable[Idx].VirtualBase = SystemMemoryBase;
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MemoryTable[Idx].Length = SystemMemoryLength;
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MemoryTable[Idx].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
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Idx++;
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// if system memory does not go to the last address (0xFFFFFFFF)
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if( SystemMemoryLastAddress < MAX_ADDRESS ) {
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MemoryTable[Idx].PhysicalBase = SystemMemoryLastAddress + 1;
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MemoryTable[Idx].VirtualBase = MemoryTable[Idx].PhysicalBase;
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MemoryTable[Idx].Length = MAX_ADDRESS - MemoryTable[Idx].PhysicalBase + 1;
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MemoryTable[Idx].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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Idx++;
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}
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// End of Table
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// End of Table
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MemoryTable[2].PhysicalBase = 0;
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MemoryTable[Idx].PhysicalBase = 0;
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MemoryTable[2].VirtualBase = 0;
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MemoryTable[Idx].VirtualBase = 0;
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MemoryTable[2].Length = 0;
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MemoryTable[Idx].Length = 0;
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MemoryTable[2].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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MemoryTable[Idx].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
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DEBUG ((EFI_D_INFO, "Enabling MMU, setting 0x%08x + %d MB to %a\n",
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SystemMemoryBase, SystemMemoryLength/1024/1024,
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(CacheAttributes == DDR_ATTRIBUTES_CACHED) ? "cacheable" : "uncacheable"));
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ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
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ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
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BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
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BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);
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@ -109,7 +163,7 @@ Returns:
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// Enable program flow prediction, if supported.
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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ArmEnableBranchPrediction ();
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JamArmMmuConfig();
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ConfigureMmu();
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return EFI_SUCCESS;
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return EFI_SUCCESS;
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}
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}
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@ -26,7 +26,7 @@
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#
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#
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# The following information is for reference only and not required by the build tools.
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# The following information is for reference only and not required by the build tools.
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#
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#
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# VALID_ARCHITECTURES = IA32 X64 IPF EBC
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# VALID_ARCHITECTURES = ARM
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#
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#
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[Sources]
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[Sources]
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