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ArmPkg/ArmLib: retrieve cache line length from CTR not CCSIDR 

The stride used by the cache maintenance by MVA instructions should
be retrieved from CTR_EL0.DminLine and CTR_EL0.IminLine, whose values
reflect the actual geometry of the caches. Using CCSIDR for this purpose
violates the architecture.

Also, move the line length accessors to common code, since there is no
need to keep them separate between ARMv7 and AArch64.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18754 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2015-11-09 13:26:52 +00:00 committed by abiesheuvel
parent f97ab1bbf4
commit fbf658ebc8
3 changed files with 18 additions and 52 deletions
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25
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
View File

@ -21,31 +21,6 @@
#include "AArch64Lib.h" #include "AArch64Lib.h"
#include "ArmLibPrivate.h" #include "ArmLibPrivate.h"
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
}
VOID VOID
AArch64DataCacheOperation ( AArch64DataCacheOperation (
IN AARCH64_CACHE_OPERATION DataCacheOperation IN AARCH64_CACHE_OPERATION DataCacheOperation

27
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@ -20,33 +20,6 @@
#include "ArmV7Lib.h" #include "ArmV7Lib.h"
#include "ArmLibPrivate.h" #include "ArmLibPrivate.h"
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (0) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
UINT32 CCSIDR = ReadCCSIDR (1) & 7;
// * 4 converts to bytes
return (1 << (CCSIDR + 2)) * 4;
// return 64;
}
VOID VOID
ArmV7DataCacheOperation ( ArmV7DataCacheOperation (
IN ARM_V7_CACHE_OPERATION DataCacheOperation IN ARM_V7_CACHE_OPERATION DataCacheOperation

18
ArmPkg/Library/ArmLib/Common/ArmLib.c
View File

@ -70,3 +70,21 @@ ArmUnsetCpuActlrBit (
Value &= ~Bits; Value &= ~Bits;
ArmWriteCpuActlr (Value); ArmWriteCpuActlr (Value);
} }
UINTN
EFIAPI
ArmDataCacheLineLength (
VOID
)
{
return 4 << ((ArmCacheInfo () >> 16) & 0xf); // CTR_EL0.DminLine
}
UINTN
EFIAPI
ArmInstructionCacheLineLength (
VOID
)
{
return 4 << (ArmCacheInfo () & 0xf); // CTR_EL0.IminLine
}