mirror of https://github.com/acidanthera/audk.git
OvmfPkg/ResetVector: Clear SEV encryption bit for non-leaf PTEs
Future changes will make use of CpuPageTableLib to handle splitting page table mappings during SEC phase. While it's not strictly required by hardware, CpuPageTableLib relies on non-leaf PTEs never having the encryption bit set, so go ahead change the page table setup code to satisfy this expectation. Suggested-by: Tom Lendacky <thomas.lendacky@amd.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
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@ -162,11 +162,14 @@ SevClearPageEncMaskForGhcbPage:
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;
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;
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; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.
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; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.
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; This requires the 2MB page for this range be broken down into 512 4KB
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; This requires the 2MB page for this range be broken down into 512 4KB
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; pages. All will be marked encrypted, except for the GHCB.
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; pages. All will be marked encrypted, except for the GHCB. Since the
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; original PMD entry is no longer a leaf entry, remove the encryption
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; bit when pointing to the PTE page.
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;
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;
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mov ecx, (GHCB_BASE >> 21)
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mov ecx, (GHCB_BASE >> 21)
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mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR
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mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000)], eax
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mov [ecx * 8 + PT_ADDR (0x2000)], eax
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mov [ecx * 8 + PT_ADDR (0x2000) + 4], strict dword 0
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;
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;
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; Page Table Entries (512 * 4KB entries => 2MB)
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; Page Table Entries (512 * 4KB entries => 2MB)
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@ -67,7 +67,7 @@ BITS 32
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;
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;
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; Create page tables for 4-level paging
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; Create page tables for 4-level paging
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;
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;
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; Argument: upper 32 bits of the page table entries
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; Argument: upper 32 bits of the leaf page table entries
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;
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;
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%macro CreatePageTables4Level 1
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%macro CreatePageTables4Level 1
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@ -78,19 +78,19 @@ BITS 32
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; Top level Page Directory Pointers (1 * 512GB entry)
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], %1
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mov dword[PT_ADDR (4)], 0
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;
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], %1
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mov dword[PT_ADDR (0x1004)], 0
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x100C)], %1
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mov dword[PT_ADDR (0x100C)], 0
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1014)], %1
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mov dword[PT_ADDR (0x1014)], 0
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x101C)], %1
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mov dword[PT_ADDR (0x101C)], 0
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;
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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; Page Table Entries (2048 * 2MB entries => 4GB)
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@ -141,7 +141,7 @@ BITS 32
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;
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;
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; Create page tables for 5-level paging with gigabyte pages
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; Create page tables for 5-level paging with gigabyte pages
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;
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;
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; Argument: upper 32 bits of the page table entries
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; Argument: upper 32 bits of the leaf page table entries
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;
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;
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; We have 6 pages available for the early page tables,
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; We have 6 pages available for the early page tables,
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; we use four of them:
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; we use four of them:
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@ -164,15 +164,15 @@ BITS 32
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; level 5
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; level 5
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], %1
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mov dword[PT_ADDR (4)], 0
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; level 4
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; level 4
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], %1
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mov dword[PT_ADDR (0x1004)], 0
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; level 3 (1x -> level 2, 3x 1GB)
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; level 3 (1x -> level 2, 3x 1GB)
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mov dword[PT_ADDR (0x3000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x3000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x3004)], %1
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mov dword[PT_ADDR (0x3004)], 0
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mov dword[PT_ADDR (0x3008)], (1 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x3008)], (1 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x300c)], %1
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mov dword[PT_ADDR (0x300c)], %1
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mov dword[PT_ADDR (0x3010)], (2 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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mov dword[PT_ADDR (0x3010)], (2 << 30) + PAGE_PDE_LARGEPAGE_ATTR
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