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MdePkg.dec: RISC-V: Define override bit for Sstc extension 

Define the BIT 1 as the override bit for Sstc extension. This will be
used by the timer driver to decide whether to use SBI calls or direct
CSR access to configure the timer.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
This commit is contained in:
Sunil V L 2024-01-03 11:13:47 +05:30 committed by mergify[bot]
parent 889535caf8
commit fd629ef6e3
1 changed files with 2 additions and 0 deletions
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MdePkg/MdePkg.dec
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@ -2405,6 +2405,8 @@
# Configurability to override RISC-V CPU Features
# BIT 0 = Cache Management Operations. This bit is relevant only if
# previous stage has feature enabled and user wants to disable it.
# BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
# previous stage has feature enabled and user wants to disable it.
#
gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69