mirror of https://github.com/acidanthera/audk.git
More disasm work.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9932 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
5e24f37a6f
commit
fef5272652
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@ -90,6 +90,14 @@ extern CHAR8 *gReg[];
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#define ADD_IMM5_2REG 228
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#define CPD_THUMB2 229
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#define THUMB2_4REGS 230
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#define ADD_IMM12_1REG 231
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#define THUMB2_IMM16 232
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#define MRC_THUMB2 233
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#define MRRC_THUMB2 234
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#define THUMB2_MRS 235
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#define THUMB2_MSR 236
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typedef struct {
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@ -210,6 +218,10 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
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{ "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
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{ "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
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{ "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
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{ "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
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{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
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{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
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{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
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@ -247,6 +259,14 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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{ "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
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{ "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
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{ "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
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{ "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
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{ "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
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{ "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR
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{ "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>
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{ "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
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{ "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
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@ -267,17 +287,17 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
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{ "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS },// SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS },// SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS },// SMLSD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS },// SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS },// SMMLA <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS },// SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS },// SMMLS <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS },// SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
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{ "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS },// USADA8 <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS },// SMLAD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS },// SMLADX <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
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{ "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>
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{ "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>
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{ "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
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@ -808,6 +828,22 @@ DisassembleThumbInstruction (
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
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return;
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case ADD_IMM12_1REG:
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// MOV{S} <Rd>, #<const> i:imm3:imm8
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if ((OpCode32 & BIT20) == BIT20) {
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Buf[Offset - 3] = 'S'; // assume %-6a
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}
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
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return;
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case THUMB2_IMM16:
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// MOVW <Rd>, #<const> i:imm3:imm8
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Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
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Target |= ((OpCode32 >> 4) & 0xf0000);
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
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return;
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case ADD_IMM5:
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// ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
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if ((OpCode32 & BIT20) == BIT20) {
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@ -891,6 +927,28 @@ DisassembleThumbInstruction (
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}
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return;
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case MRC_THUMB2:
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// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
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coproc = (OpCode32 >> 8) & 0xf;
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opc1 = (OpCode32 >> 20) & 0xf;
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opc2 = (OpCode32 >> 5) & 0x7;
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CRn = (OpCode32 >> 16) & 0xf;
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CRm = OpCode32 & 0xf;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);
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if (opc2 != 0) {
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AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);
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}
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return;
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case MRRC_THUMB2:
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// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
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coproc = (OpCode32 >> 8) & 0xf;
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opc1 = (OpCode32 >> 20) & 0xf;
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CRn = (OpCode32 >> 16) & 0xf;
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CRm = OpCode32 & 0xf;
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Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);
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return;
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case THUMB2_2REGS:
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// <Rd>, <Rm>
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
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@ -901,6 +959,17 @@ DisassembleThumbInstruction (
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
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return;
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case THUMB2_MRS:
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// MRS <Rd>, CPSR
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AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
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return;
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case THUMB2_MSR:
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// MRS CPSR_<fields>, <Rd>
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Target = (OpCode32 >> 10) & 3;
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AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "":"f", (Target & 1) == 0 ? "":"s", gReg[Rd]);
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return;
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case THUMB2_NO_ARGS:
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default:
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break;
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