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ArmPkg: Fix various typos

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Fix various typos in ArmPkg.

Signed-off-by: Coeur <coeur@gmx.fr>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Antoine Cœur 2019-02-06 23:39:35 +08:00 committed by Leif Lindholm
parent 080981d72d
commit ff5fef1428
31 changed files with 62 additions and 62 deletions
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2
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c
View File

@ -146,7 +146,7 @@ CpuIoCheckParameter (
//
// Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
// can also be the maximum integer value supported by the CPU, this range
// check must be adjusted to avoid all oveflow conditions.
// check must be adjusted to avoid all overflow conditions.
//
// The following form of the range check is equivalent but assumes that
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).

2
ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c
View File

@ -281,7 +281,7 @@ GetMemoryRegionRec (
BlockEntry++;
} else if (EntryType == BlockEntryType) {
// We have found the BlockEntry attached to the address. We save its start address (the start
// address might be before the 'BaseAdress') and attributes
// address might be before the 'BaseAddress') and attributes
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);
*RegionLength = 0;
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;

2
ArmPkg/Drivers/CpuDxe/Arm/Mmu.c
View File

@ -234,7 +234,7 @@ SyncCacheConfig (
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));
DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));
// This code assumes MMU is enabled and filed with section translations
ASSERT (ArmMmuEnabled ());

2
ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
View File

@ -188,7 +188,7 @@ CpuSetMemoryAttributes (
if ((BaseAddress & (SIZE_4KB - 1)) != 0) {
// Minimum granularity is SIZE_4KB (4KB on ARM)
DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));
DEBUG ((DEBUG_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum granularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));
return EFI_UNSUPPORTED;
}

4
ArmPkg/Drivers/CpuDxe/CpuMpCore.c
View File

@ -61,7 +61,7 @@ PublishArmProcessorTable (
// Allocate Runtime memory for ARM processor table
ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));
// Check if the memory allocation is succesful or not
// Check if the memory allocation is successful or not
ASSERT(NULL != ArmProcessorTable);
// Set ARM processor table to default values
@ -81,7 +81,7 @@ PublishArmProcessorTable (
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (
ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));
// Check if the memory allocation is succesful or not
// Check if the memory allocation is successful or not
ASSERT(NULL != ArmProcessorTable->ArmCpus);
// Copy ARM Processor Table data from HOB list to newly allocated memory

2
ArmPkg/Drivers/CpuDxe/Exception.c
View File

@ -27,7 +27,7 @@ InitializeExceptions (
VectorInfo = VectorInfoList;
}
// intialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
// initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
InitializeCpuExceptionHandlers(VectorInfo);
Status = EFI_SUCCESS;

2
ArmPkg/Drivers/CpuPei/CpuPei.c
View File

@ -23,7 +23,7 @@ Abstract:
//
#include <PiPei.h>
//
// The protocols, PPI and GUID defintions for this module
// The protocols, PPI and GUID definitions for this module
//
#include <Ppi/ArmMpCoreInfo.h>

2
ArmPkg/Drivers/TimerDxe/TimerDxe.c
View File

@ -365,7 +365,7 @@ TimerInitialize (
UINT32 TimerHypIntrNum;
if (ArmIsArchTimerImplemented () == 0) {
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n"));
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence can't use this Driver \n"));
ASSERT (0);
}

2
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
View File

@ -691,7 +691,7 @@ FileGetPosition (
@param[in] Position The byte position from the start of the file to set.
@retval EFI_SUCCESS The position was set.
@retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed.
@retval EFI_DEVICE_ERROR The semi-hosting positioning operation failed.
@retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open
directories.
@retval EFI_INVALID_PARAMETER The parameter "This" is NULL.

2
ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
View File

@ -157,7 +157,7 @@ FileGetPosition (
@param[in] Position The byte position from the start of the file to set.
@retval EFI_SUCCESS The position was set.
@retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed.
@retval EFI_DEVICE_ERROR The semi-hosting positioning operation failed.
@retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open
directories.

4
ArmPkg/Include/Library/ArmDisassemblerLib.h
View File

@ -10,8 +10,8 @@
#define __ARM_DISASSEBLER_LIB_H__
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.

2
ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
View File

@ -152,7 +152,7 @@ MicroSecondDelay (
@param NanoSeconds The minimum number of nanoseconds to delay.
@return The value of NanoSeconds inputed.
@return The value of NanoSeconds inputted.
**/
UINTN

2
ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c
View File

@ -13,7 +13,7 @@
#include <Library/ArmDisassemblerLib.h>
/**
Place a disassembly of of **OpCodePtr into buffer, and update OpCodePtr to
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@param OpCodePtrPtr Pointer to pointer of instruction to disassemble.

4
ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c
View File

@ -137,8 +137,8 @@ RotateRight (
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.

14
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c
View File

@ -1,5 +1,5 @@
/** @file
Thumb Dissassembler. Still a work in progress.
Thumb Disassembler. Still a work in progress.
Wrong output is a bug, so please fix it.
Hex output means there is not yet an entry or a decode bug.
@ -103,7 +103,7 @@ typedef struct {
} THUMB_INSTRUCTIONS;
THUMB_INSTRUCTIONS gOpThumb[] = {
// Thumb 16-bit instrucitons
// Thumb 16-bit instructions
// Op Mask Format
{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
{ "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
@ -447,7 +447,7 @@ SignExtend32 (
//
// Some instructions specify the PC is always considered aligned
// The PC is after the instruction that is excuting. So you pass
// The PC is after the instruction that is executing. So you pass
// in the instruction address and you get back the aligned answer
//
UINT32
@ -459,8 +459,8 @@ PCAlign4 (
}
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.
@ -1023,8 +1023,8 @@ DisassembleArmInstruction (
/**
Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
point to next instructin.
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
We cheat and only decode instructions that access
memory. If the instruction is not found we dump the instruction in hex.

2
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.S
View File

@ -227,7 +227,7 @@ ASM_PFX(AsmCommonExceptionEntry):
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
@ Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) {
cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
cmp r4, #1 @ // UND & SVC have different LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry

2
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
View File

@ -221,7 +221,7 @@ AsmCommonExceptionEntry
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {
cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb
cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry

4
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c
View File

@ -94,7 +94,7 @@ InitializeCpuExceptionHandlers(
Status = EFI_SUCCESS;
// if we are requested to copy exceptin handlers to another location
// if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) {
VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
@ -131,7 +131,7 @@ InitializeCpuExceptionHandlers(
}
/**
Copies exception handlers to the speciifed address.
Copies exception handlers to the specified address.
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.

6
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
View File

@ -430,13 +430,13 @@ ASM_FUNC(ArmReadMpidr)
ret
// Keep old function names for C compatibilty for now. Change later?
// Keep old function names for C compatibility for now. Change later?
ASM_FUNC(ArmReadTpidrurw)
mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
ret
// Keep old function names for C compatibilty for now. Change later?
// Keep old function names for C compatibility for now. Change later?
ASM_FUNC(ArmWriteTpidrurw)
msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
ret
@ -453,7 +453,7 @@ ASM_FUNC(ArmReadIdPfr0)
ret
// Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
// Q: id_aa64pfr1_el1 not defined yet. What does this function want to access?
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
// See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
// Not defined yet, but stick in here for now, should read all zeros.

2
ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
View File

@ -23,7 +23,7 @@
ASM_FUNC(ArmIsMpCore)
mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
mrs x0, mpidr_el1 // Read EL1 Multiprocessor Affinty Reg (MPIDR)
and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
lsr x0, x0, #MPIDR_U_BIT
eor x0, x0, #1

2
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
View File

@ -352,7 +352,7 @@ UpdateRegionMapping (
do {
// Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
// such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
// such as the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
BlockEntrySize = RegionLength;
BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
if (BlockEntry == NULL) {

2
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
View File

@ -691,7 +691,7 @@ UpdateSectionEntries (
for(i=0; i<NumSections; i++) {
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
// has this descriptor already been coverted to pages?
// has this descriptor already been converted to pages?
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
// forward this 1MB range to page table function instead
Status = UpdatePageEntries (

2
ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
View File

@ -1,5 +1,5 @@
#/** @file
# PeCoff extra action libary for DXE phase that run Unix emulator.
# PeCoff extra action library for DXE phase that run Unix emulator.
#
# Lib to provide memory journal status code reporting Routines
# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>

2
ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c
View File

@ -137,7 +137,7 @@ BaseName (
/**
This is the default action to take on an unexpected exception
Since this is exception context don't do anything crazy like try to allcoate memory.
Since this is exception context don't do anything crazy like try to allocate memory.
@param ExceptionType Type of the exception
@param SystemContext Register state at the time of the Exception

2
ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c
View File

@ -168,7 +168,7 @@ STATIC CHAR8 *gExceptionTypeString[] = {
/**
This is the default action to take on an unexpected exception
Since this is exception context don't do anything crazy like try to allcoate memory.
Since this is exception context don't do anything crazy like try to allocate memory.
@param ExceptionType Type of the exception
@param SystemContext Register state at the time of the Exception

4
ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c
View File

@ -650,11 +650,11 @@ HandleCapsules (
Do the platform specific action after the console is ready
Possible things that can be done in PlatformBootManagerAfterConsole:
> Console post action:
> Dynamically switch output mode from 100x31 to 80x25 for certain senarino
> Dynamically switch output mode from 100x31 to 80x25 for certain scenario
> Signal console ready platform customized event
> Run diagnostics like memory testing
> Connect certain devices
> Dispatch aditional option roms
> Dispatch additional option roms
> Special boot: e.g.: USB boot, enter UI
**/
VOID

2
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c
View File

@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
/**
Append string to debugger script file, create file if needed.
This library can show up in mulitple places so we need to append the file every time we write to it.
This library can show up in multiple places so we need to append the file every time we write to it.
For example Sec can use this to load the DXE core, and the DXE core would use this to load all the
other modules. So we have two instances of the library in the system.

2
ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
View File

@ -1,5 +1,5 @@
#/** @file
# PeCoff extra action libary for DXE phase that run Unix emulator.
# PeCoff extra action library for DXE phase that run Unix emulator.
#
# Lib to provide memory journal status code reporting Routines
# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>

32
ArmPkg/Library/SemiHostingDebugLib/DebugLib.c
View File

@ -172,11 +172,11 @@ DebugBPrint (
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if
DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then
CpuDeadLoop() is called. If neither of these bits are set, then this function
returns immediately after the message is printed to the debug output device.
DebugAssert() must actively prevent recusrsion. If DebugAssert() is called while
DebugAssert() must actively prevent recursion. If DebugAssert() is called while
processing another DebugAssert(), then DebugAssert() must return immediately.
If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.
@ -246,7 +246,7 @@ DebugClearMemory (
ASSERT (Buffer != NULL);
//
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer
// SetMem() checks for the ASSERT() condition on Length and returns Buffer
//
return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
}
@ -257,10 +257,10 @@ DebugClearMemory (
Returns TRUE if ASSERT() macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
PcdDebugPropertyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.
@retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@ -278,10 +278,10 @@ DebugAssertEnabled (
Returns TRUE if DEBUG()macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
PcdDebugPropertyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.
@retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@ -299,10 +299,10 @@ DebugPrintEnabled (
Returns TRUE if DEBUG_CODE()macros are enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
PcdDebugPropertyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN
@ -320,10 +320,10 @@ DebugCodeEnabled (
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of
PcdDebugProperyMask is set. Otherwise FALSE is returned.
PcdDebugPropertyMask is set. Otherwise FALSE is returned.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.
@retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set.
@retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear.
**/
BOOLEAN

2
ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
View File

@ -1,5 +1,5 @@
#/** @file
# Semihosting serail port lib
# Semihosting serial port lib
#
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>
#

8
ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c
View File

@ -103,7 +103,7 @@ SerialPortWrite (
@param NumberOfBytes Number of output bytes which are cached in Buffer.
@retval 0 Read data failed.
@retval !0 Aactual number of bytes read from serial device.
@retval !0 Actual number of bytes read from serial device.
**/
UINTN
@ -120,10 +120,10 @@ SerialPortRead (
/**
Check to see if any data is avaiable to be read from the debug device.
Check to see if any data is available to be read from the debug device.
@retval TRUE At least one byte of data is avaiable to be read
@retval FALSE No data is avaiable to be read
@retval TRUE At least one byte of data is available to be read
@retval FALSE No data is available to be read
**/
BOOLEAN