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MdeModulePkg/PciBusDxe: recognize hotplug-capable PCIe ports 

Section 7.8.2 of the PCI Express specification (r4.0 v0.3), entitled "PCI
Express Capabilities Register (Offset 02h)", and section 7.8.9 "Slot
Capabilities Register (Offset 14h)" of the same, describe the conditions
when a PCIe port should be considered "supporting hotplug":

- it should be a root complex port or a switch downstream port, and

- it should have the "Slot Implemented" bit set in the Express
  Capabilities Register, and

- it should have the "Hot-Plug Capable" bit set in the Slot Capabilities
  Register.

The first two sub-conditions are already implemented in at least two open
source projects I could find:

- in SeaBIOS by Marcel Apfelbaum: "hw/pci: reserve IO and mem for pci
  express downstream ports with no devices attached"
  <https://code.coreboot.org/p/seabios/source/commit/3aa31d7d6375>,

- in edk2 itself, in the implementation of the "PCI" UEFI Shell command:
  see the "PcieExplainTypeSlot" case label in function
  PciExplainPciExpress(), file
  "ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c".

PciBusDxe recognizes such PCIe ports as bridges, but it doesn't realize
they support hotplug. In turn PciBusDxe omits getting any resource padding
information from the platform's EFI_PCI_HOT_PLUG_INIT_PROTOCOL for these
bridges:

  GatherPpbInfo()                [PciEnumeratorSupport.c]
    GetResourcePaddingPpb()      [PciResourceSupport.c]
      GetResourcePaddingForHpb() [PciHotPlugSupport.c]
        IsPciHotPlugBus()        [PciHotPlugSupport.c]
          //
          // returns FALSE
          //
        //
        // the following is not reached:
        //
        gPciHotPlugInit->GetResourcePadding()

Implement a function called SupportsPcieHotplug() for identifying such
ports, and call it from IsPciHotPlugBus() (after the call to IsSHPC()).

Cc: "Johnson, Brian J." <bjohnson@sgi.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
This commit is contained in:
Laszlo Ersek 2016-07-01 01:12:29 +02:00
parent c6b5fb7386
commit ffdd337630
2 changed files with 117 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

96
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.c
View File

@ -316,6 +316,94 @@ IsSHPC (
return FALSE;
}
/**
Check whether PciIoDevice supports PCIe hotplug.
This is equivalent to the following condition:
- the device is either a PCIe switch downstream port or a root port,
- and the device has the SlotImplemented bit set in its PCIe capability
register,
- and the device has the HotPlugCapable bit set in its slot capabilities
register.
@param[in] PciIoDevice The device being checked.
@retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.
@retval FALSE Otherwise.
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
)
{
UINT32 Offset;
EFI_STATUS Status;
PCI_REG_PCIE_CAPABILITY Capability;
PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
if (PciIoDevice == NULL) {
return FALSE;
}
//
// Read the PCI Express Capabilities Register
//
if (!PciIoDevice->IsPciExp) {
return FALSE;
}
Offset = PciIoDevice->PciExpressCapabilityOffset +
OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability);
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint16,
Offset,
1,
&Capability
);
if (EFI_ERROR (Status)) {
return FALSE;
}
//
// Check the contents of the register
//
switch (Capability.Bits.DevicePortType) {
case PCIE_DEVICE_PORT_TYPE_ROOT_PORT:
case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT:
break;
default:
return FALSE;
}
if (!Capability.Bits.SlotImplemented) {
return FALSE;
}
//
// Read the Slot Capabilities Register
//
Offset = PciIoDevice->PciExpressCapabilityOffset +
OFFSET_OF (PCI_CAPABILITY_PCIEXP, SlotCapability);
Status = PciIoDevice->PciIo.Pci.Read (
&PciIoDevice->PciIo,
EfiPciIoWidthUint32,
Offset,
1,
&SlotCapability
);
if (EFI_ERROR (Status)) {
return FALSE;
}
//
// Check the contents of the register
//
if (SlotCapability.Bits.HotPlugCapable) {
return TRUE;
}
return FALSE;
}
/**
Get resource padding if the specified PCI bridge is a hot plug bus.
@ -382,6 +470,14 @@ IsPciHotPlugBus (
return TRUE;
}
if (SupportsPcieHotplug (PciIoDevice)) {
//
// If the PPB is a PCIe root complex port or a switch downstream port, and
// implements a hot-plug capable slot, then also return TRUE.
//
return TRUE;
}
//
// Otherwise, see if it is a Root HPC
//

21
MdeModulePkg/Bus/Pci/PciBusDxe/PciHotPlugSupport.h
View File

@ -176,6 +176,27 @@ IsSHPC (
IN PCI_IO_DEVICE *PciIoDevice
);
/**
Check whether PciIoDevice supports PCIe hotplug.
This is equivalent to the following condition:
- the device is either a PCIe switch downstream port or a root port,
- and the device has the SlotImplemented bit set in its PCIe capability
register,
- and the device has the HotPlugCapable bit set in its slot capabilities
register.
@param[in] PciIoDevice The device being checked.
@retval TRUE PciIoDevice is a PCIe port that accepts a hotplugged device.
@retval FALSE Otherwise.
**/
BOOLEAN
SupportsPcieHotplug (
IN PCI_IO_DEVICE *PciIoDevice
);
/**
Get resource padding if the specified PCI bridge is a hot plug bus.