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5 Commits

Author SHA1 Message Date
Mikhail Krichanov
98f13417fb CpuArchLib: Specified IdtTable size precisely. 2025-04-14 13:00:53 +03:00
Mikhail Krichanov
0e14a53096 Ring3: Added Idt to User page table. 2025-04-14 13:00:53 +03:00
Mikhail Krichanov
51447148b0 Ring3: Added support for separate User address space. 2025-04-14 12:50:53 +03:00
Mikhail Krichanov
2fa2894bbd Ring3: Added GetMemoryAttributes() into EFI_CPU_ARCH_PROTOCOL. 2025-04-14 11:21:17 +03:00
Mikhail Krichanov
20dd836214 MdeModulePkg/Core/Dxe: Integrate CPU Architectural producer 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223

In the current design, memory protection is not available till CpuDxe
is loaded. To resolve this, introduce CpuArchLib to move the
CPU Architectural initialization to DxeCore.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Vitaly Cheptsov <vit9696@protonmail.com>
Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
 2025-04-07 12:23:28 +03:00