7 Commits

Author SHA1 Message Date
Mikhail Krichanov
bf581dc3ce CpuArchLib: Fixed CpuGetMemoryAttributes(). 2025-04-14 13:00:53 +03:00
Mikhail Krichanov
1d3f665282 Ring3: Added support for User page table to AllocatePages(), FreePages(). 2025-04-14 13:00:53 +03:00
Mikhail Krichanov
51447148b0 Ring3: Added support for separate User address space. 2025-04-14 12:50:53 +03:00
Mikhail Krichanov
2fa2894bbd Ring3: Added GetMemoryAttributes() into EFI_CPU_ARCH_PROTOCOL. 2025-04-14 11:21:17 +03:00
Mikhail Krichanov
1a88ba5afc Ring3: Set USER bit in all page table structures. 2025-04-14 11:21:17 +03:00
Mikhail Krichanov
33f15b44de Ring3: Added EFI_MEMORY_USER attribute. 2025-04-14 11:21:14 +03:00
Mikhail Krichanov
20dd836214 MdeModulePkg/Core/Dxe: Integrate CPU Architectural producer
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223

In the current design, memory protection is not available till CpuDxe
is loaded. To resolve this, introduce CpuArchLib to move the
CPU Architectural initialization to DxeCore.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Vitaly Cheptsov <vit9696@protonmail.com>
Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
2025-04-07 12:23:28 +03:00