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5 Commits

Author SHA1 Message Date
Mikhail Krichanov
85070fbba0 CpuArchLib: Specified IdtTable size precisely. 2024-12-05 12:35:16 +03:00
Mikhail Krichanov
63dcc29d15 Ring3: Added Idt to User page table. 2024-11-29 19:40:26 +03:00
Mikhail Krichanov
3b8cd407d3 Ring3: Added support for separate User address space. 2024-11-26 19:12:15 +03:00
Mikhail Krichanov
db50e4edf1 Ring3: Added GetMemoryAttributes() into EFI_CPU_ARCH_PROTOCOL. 2024-09-03 13:10:44 +03:00
Mikhail Krichanov
769c333a61 MdeModulePkg/Core/Dxe: Integrate CPU Architectural producer 
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3223

In the current design, memory protection is not available till CpuDxe
is loaded. To resolve this, introduce CpuArchLib to move the
CPU Architectural initialization to DxeCore.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Vitaly Cheptsov <vit9696@protonmail.com>
Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
 2024-07-22 13:47:18 +03:00