Commit Graph

3 Commits

Author SHA1 Message Date
Jeff Fan dc99315b87 UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned buffer
Update MSRs semaphores to the ones in allocated aligned semaphores
buffer. If MSRs semaphores is not enough, allocate one page more.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:22 -07:00
Jeff Fan 695e62d141 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphores
Allocate MSRs semaphores in allocated aligned semaphores buffer.
And add it into semaphores structure.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:17 -07:00
Michael Kinney 529a5a8609 UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 files
Add module that initializes a CPU for the SMM environment and
installs the first level SMI handler.  This module along with the
SMM IPL and SMM Core provide the services required for
DXE_SMM_DRIVERS to register hardware and software SMI handlers.

CPU specific features are abstracted through the SmmCpuFeaturesLib

Platform specific features are abstracted through the
SmmCpuPlatformHookLib

Several PCDs are added to enable/disable features and configure
settings for the PiSmmCpuDxeSmm module

Changes between [PATCH v1] and [PATCH v2]:
1) Swap PTE init order for QEMU compatibility.
   Current PTE initialization algorithm works on HW but breaks QEMU
   emulator.  Update the PTE initialization order to be compatible
   with both.
2) Update comment block that describes 32KB SMBASE alignment requirement
   to match contents of Intel(R) 64 and IA-32 Architectures Software
   Developer's Manual
3) Remove BUGBUG comment and call to ClearSmi() that is not required.
   SMI should be cleared by root SMI handler.

[jeff.fan@intel.com: Fix code style issues reported by ECC]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>

[pbonzini@redhat.com: InitPaging: prepare PT before filling in PDE]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18645 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19 19:12:53 +00:00