When allocating memory to perform non-coherent DMA, use the cache
writeback granule rather than the data cache linesize for alignment.
This prevents the explicit cache maintenance from corrupting
unrelated adjacent data if the cache writeback granule exceeds
the cache linesize.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18759 6f19259b-4bc3-4df7-8a09-765794883524
EFI_MEMORY_UC is mapped to Strongly Ordered memory while EFI_MEMORY_WC is
mapped to Uncached Normal/System memory.
This change improve performance while accessing uncached regions in the
System Memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <oliviermartin@arm.com
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13693 6f19259b-4bc3-4df7-8a09-765794883524
Some coherencies issues were existing in the former version of DmaLib.
These issues could have for consequences to not make the MdeModulePkg/Bus/Usb
software stack not work.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12137 6f19259b-4bc3-4df7-8a09-765794883524
Ard Biesheuvel
Ronald Cron
Olivier Martin
oliviermartin
andrewfish