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7 Commits

Author SHA1 Message Date
Liming Gao 7367cc6c24 UefiCpuPkg: Clean up source files 
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
 2018-06-28 11:19:53 +08:00
Michael Kinney e9cd66d085 MdePkg/BaseXApicX2ApicLib: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESS 
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
 2015-04-27 19:48:00 +00:00
Shumin Qiu c4bac158b3 Refine the format of PCD in INF files for UefiCpuPkg. 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shumin Qiu <shumin.qiu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16617 6f19259b-4bc3-4df7-8a09-765794883524
 2015-01-16 05:20:31 +00:00
Gao, Liming e48e07424a UefiCpuPkg: INF/DEC file updates to EDK II packages 
1. Usage information in INF file comment blocks are either incomplete or incorrect.  
This includes usage information for Protocols/PPIs/GUIDs/PCDs/HOBs/Events/BootModes.  
The syntax for usage information in comment blocks is defined in the EDK II Module Information (INF) Specification

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gao, Liming <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15933 6f19259b-4bc3-4df7-8a09-765794883524
 2014-08-28 05:09:12 +00:00
Jeff Fan cf1eb6e6f8 Introduce one PCD PcdCpuInitIpiDelayInMicroSeconds to specify the delay value after sending out INIT IPI instead of hard code 10 MicroSeconds. 
Its default value is 10 millisecond per IA32 manual.
Platform could customize this PCD value for performance requirement.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
 

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15650 6f19259b-4bc3-4df7-8a09-765794883524
 2014-07-10 02:12:27 +00:00
vanjeff a66e0c7da7 1. Added SetLocalApicBaseAdress() and GetLocalApicBaseAddress() APIs in Local APIC library. 
2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress.

Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
Reviewed-by: Rui Sun <rui.sun@intel.com>



 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524
 2012-08-23 01:42:01 +00:00
rsun3 bf73cc4bbc Add Local APIC Library class defining APIs for common Local APIC operations. Add two Local APIC library instances, one is for xAPIC mode only, the other is for x2APIC capable processors which have xAPIC and x2APIC modes. 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10814 6f19259b-4bc3-4df7-8a09-765794883524
 2010-08-23 06:34:39 +00:00