Make the comments align with the function.
And add some missing function comments.
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
NULL pointer detection is done by making use of paging mechanism of CPU.
During page table setup, if enabled, the first 4-K page (0-4095) will be
marked as NOT PRESENT. Any code which unintentionally access memory between
0-4095 will trigger a Page Fault exception which warns users that there's
potential illegal code in BIOS.
This also means that legacy code which has to access memory between 0-4095
should be cautious to temporarily disable this feature before the access
and re-enable it afterwards; or disalbe this feature at all.
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ayellet Wolman <ayellet.wolman@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
PI1.4a spec added "For S3 resume boot modes DXE IPL must be
prepared to execute without permanent memory installed and
invoke the S3 resume modules."
To follow PI1.4a spec, this patch is to update DxeIpl and
PeiCore to enable S3 resume from temporary memory.
The normal boot path still enforces the permanent memory
requirement.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Tested-by: Katie Dellaquila <katie.dellaquila@hp.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2. DxeMain will get Vector Handoff Table GUIDed HOB to install configuration table if it has.
3. Updated CPU Exception Handler Library to provide 3 new APIs to replace original one API and updated NULL instance accordingly.
4. Updated DxeMain/CapsuleX64/BootSriptExectorDxe to use the new API in CPU Exception Handler Lib.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14884 6f19259b-4bc3-4df7-8a09-765794883524
2. Update DxeIpl PEIM to not use S3Lib and RecoveryLib since the dependent PPIs have been moved from IntelFrameworkPkg to MdePkg. This will help to reduce the library instance selection in platform DSC files.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9046 6f19259b-4bc3-4df7-8a09-765794883524
1) PeiMain:
- Use PCD for bundle of status code which definitions are put into MdePkg.dec file.
2) DxeMain:
- Use PCD for bundle of status code which definitions are put into MdePkg.dec file.
- Do not produce SectionExtraction protocol which is belong to IntelFramework specification.
- Update many macro for PI specifications.
3) DxeIpl
- Use PCD for bundle of status code which definitions are put into MdePkg.dec file.
4) Add SectionExtractionDxe module (IntelFrameworkModulePkg)
- This module will produce EFI_SECTION_EXTRACTION_PROTOCOL defined in framework specification. If a old platform want to use this protocol, then this platform need dispatch this DXE driver.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4376 6f19259b-4bc3-4df7-8a09-765794883524
2. Add PeiDxeExtractGuidedSectionLib library instance and one PCD PcdMaximumGuidedExtractHandler in MdePkg.
3. Update DxeIpl and DxeMain to consume new library.
4. Update BaseUefiTianoCustomDecompressLib to register TianoDecomress extractguidedsection handler.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@3980 6f19259b-4bc3-4df7-8a09-765794883524