Commit Graph

5 Commits

Author SHA1 Message Date
Tycho Nightingale 97be280174 PcAtChipsetPkg: Enable timer interrupt through I/O APIC
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15576 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-20 07:18:08 +00:00
rsun3 9ff904b046 PcAtChipsetPkg HPET Timer DXE Driver: Update CPU Arch Protocol.SetTimerPeriod() to program HPET/IOAPIC register with APIC ID of current BSP in case the BSP has been switched.
Signed-off-by: rsun3
Reviewed-by: li-elvin


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12778 6f19259b-4bc3-4df7-8a09-765794883524
2011-11-25 01:59:50 +00:00
li-elvin 22fde64e92 HPET driver was updated and included:
Comparator register automatically grow without breaking main counter register, this allow other driver to use HPET main counter.
Timer register overflow handle.
32-bit HPET timer support.
TimerDriverSetTimerPeriod is changed to handle HPET timer interrupt delivered into real mode.

Signed-off-by: li-elvin
Reviewed-by: vanjeff


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12700 6f19259b-4bc3-4df7-8a09-765794883524
2011-11-15 07:58:00 +00:00
mdkinney 0cdda8d6f0 Add generic HPET Timer DXE Driver and support libraries.
Minor update to logic to prevent writing a the read-only MSI Capability bit with 0 when HPET supports MSIs

Signed-off-by: mdkinney
Reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12272 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-02 15:30:54 +00:00
mdkinney 986d1dfb08 Add generic HPET Timer DXE Driver and support libraries
Signed-off-by: mdkinney
Reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12260 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-02 02:43:51 +00:00