Commit Graph

8 Commits

Author SHA1 Message Date
Chasel, Chiu 12a0a80b4a IntelFsp2Pkg: FSP can utilize bootloader stack
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485

Current FSP utilizes pre-allocated temporary memory from
boot loader for both heap and stack. To reduce overall
temporary memory usage FSP may share the same stack with
boot loader and only needs a smaller memory for heap,
no separate memory required for stack.
Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing
stack with boot loader, in this case boot loader stack
has to be large enough for FSP to use. Default is 50
(half memory heap and half memory stack) for backward
compatible with original model.

Test: Verified on internal platform and booting successfully
      with both modes.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2019-01-28 15:49:13 +08:00
Chasel, Chiu c09b254bdc IntelFsp2Pkg: Fixed potentially NULL pointer accessing
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1280

When copying IDT table in SecMain, the pointer might be
NULL so added the check to fix it.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
2018-10-29 11:24:58 +08:00
Chasel, Chiu 901ae29dfe IntelFsp2Pkg: Fix GCC49/XCODE build failure
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1276

Fixed potentially uninitialized variable build failure
caused by commit: b1cc6f672f

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-10-26 11:34:21 +08:00
Chasel, Chiu b1cc6f672f IntelFsp2Pkg: FSP should not override IDT
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265

FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.
To mitigate temporary memory usage a PCD
PcdFspMaxInterruptSupported created for platform to decide
how many interrupts the FSP IDT table can support.

Test: Verified on internal platform and boots successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-10-25 17:01:36 +08:00
Chasel, Chiu a2e61f341d IntelFsp2Pkg: Support FSP Dispatch mode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241

Add support for both API (original mode) and DISPATCH mode:
1. Add FspMode field from reserved byte of Global
   Data Structure to tell which mode is selected by boot
   loader. If boot loader invoking FSP-M API this field
   will remain as default 0 (API mode), otherwise platform
   FSP should set this field to 1 (Dispatch mode) when
   initializing Global Data Structure.
2. gFspInApiModePpiGuid will be instaled when FSP running in API
   mode and modules only for API mode should have this in depex.
3. If it is DISPATCH mode, FSP will return to PEI dispatcher,
   not directly return to boot loader.
4. DISPATCH mode supports DXE NotifyPhase drivers so FSP
   will not wait for PEI NotifyPhase callbacks, instead it
   will install gFspReadyForNotifyPhasePpiGuid PPI for
   platform to complete late initialization before transferring
   to DXE.

Test: Verified FSP API and DISPATCH modes on 2 internal
      platforms and both boot successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-10-19 15:01:00 +08:00
Liming Gao e37bb20c7b IntelFsp2Pkg: Clean up source files
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-06-28 11:19:43 +08:00
Gary Lin 058dcbf2b2 IntelFsp2Pkg: Fix typos in comments
- tempory -> temporary
- immediatly -> immediately
- permenent -> permanent
- funciton -> function

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-24 09:26:31 +08:00
Jiewen Yao cf1d454983 Add IntelFsp2Pkg and IntelFsp2WrapperPkg.
Add FSP2.0 support.
This series of patch is to support FSP2.0 specification at
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf

Some major updates include:
1) One FSP binary is separated to multiple components:
FSP-T, FSP-M, FSP-S, and optional FSP-O.
Each component has its own configuration data region.
2) All FSP-APIs use same UPD format - FSP_UPD_HEADER.
3) Add EnumInitPhaseEndOfFirmware notifyphase.
4) FSP1.1/FSP1.0 compatibility is NOT maintained.
5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg,
to indicate that it is for FspWrapper only.

IntelFspPkg and IntelFspWrapperPkg will be deprecated.
The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg
and IntelFsp2WrapperPkg.
The old platform can still use IntelFspPkg and IntelFspWrapperPkg
for compatibility consideration.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
2016-05-13 13:00:53 +08:00