BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1679
The checking to CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI is enough,
the checking to CPU generation could be removed, then the code
could be reused by more platforms.
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621
According to Intel SDM as below, the BIT0 should be treated as
lock bit, and BIT1 should be treated as disable(1)/enable(0) bit.
"11b: AES instructions are not available until next
RESET.
Otherwise, AES instructions are available.
If the configuration is not 01b, AES
instructions can be mis-configured if a privileged agent
unintentionally writes 11b"
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
With correct model CPU, current checking logic will
always execute AsmReadMsr64 operation and then check
ECX.AESNI[bit 25] = 1. Update checking logic to check
ECX.AESNI[bit 25] = 1 first and then do AsmReadMsr64
operation.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Bell Song <binx.song@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
The ConfigData parameter initialized in *GetConfigData function should not be NULL in
later *Support, *Initilize function, so just add ASSERT code check in these functions.
Cc: Ming Shao <ming.shao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).
Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.
v2:
1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
MSR_IA32_MISC_ENABLE.
2. Fix bug that SMX and VMX feature is swapped.
v3:
1. Add AesniGetConfigData() to get current register state.
v5:
Move MSR reading from AesniGetConfigData() to AesniSupport().
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Star Zeng
Michael D Kinney
Song, BinX
Eric Dong
Jeff Fan