The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm2.asm to Ia32/WriteMm2.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm3.asm to Ia32/WriteMm3.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm4.asm to Ia32/WriteMm4.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm5.asm to Ia32/WriteMm5.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm6.asm to Ia32/WriteMm6.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/WriteMm7.asm to Ia32/WriteMm7.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/Wbinvd.asm to Ia32/Wbinvd.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/RdRand.asm to Ia32/RdRand.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/EnablePaging64.asm to Ia32/EnablePaging64.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/DivU64x64Remainder.asm to Ia32/DivU64x64Remainder.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
These routines are defined in GccInline.c.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
This helps generate proper code when converted to NASM, and there is
also no reason for this symbol to be public.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Once the MASM code is converted to NASM, it will be linked into GCC
builds. Since GccInline.c provides these routines for GCC, we need to
prevent this linking.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
NASM wants this code to specify a size.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
NASM doesn't support EXTERNDEF, so convert this to EXTERN.
This will make it easier to convert this code to NASM using an
automated script.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
When we try to cd up two levels using the "../.." notation we
only go up one level. This patch fix this bug.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Add UnicodeStrToAsciiStrS() and AsciiStrToUnicodeStrS() API.
These 2 safe version APIs are used to replace UnicodeStrToAsciiStr() and
AsciiStrToUnicodeStr() API.
The safe version string convert APIs use similar check as StrCpyS().
Cc: Liming Gao <Liming.Gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <Jiewen.Yao@intel.com>
Reviewed-by: Liming Gao <Liming.Gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Add more comments:
1) EDKII version safe string function is similar as the one C11.
2) If error is returned, the Destination is unmodified.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
There is absolutely no reason to artificially limit the SKU range to 1-255.
PI1.4a spec fixed the artificial limitation.
This patch is to follow PI1.4a spec to remove PCD_MAX_SKU_ID definition,
the check to PCD_MAX_SKU_ID and the comments describes the limitation.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This patch adds more check in SmmIsBufferOutsideSmmValid(), to make sure that
SMM communication buffer is only EfiReservedMemoryType/EfiRuntimeServicesCode/
EfiRuntimeServicesData/EfiACPIMemoryNVS. So that the communication buffer will
not touch any OS memory.
The assumption is that a platform reports valid SMM communication buffer at
EndOfDxe, because EndOfDxe is last hook point that SMM code can call-out to
get memory map information.
A platform MUST finish SMM communication buffer allocation before EndOfDxe.
If a DXE or OS driver need do communication after EndOfDxe, it can either
allocate SMM communication buffer before EndOfDxe and save it, or consume
EDKII_PI_SMM_COMMUNICATION_REGION_TABLE table to get general fixed comm buffer.
This is designed to meet Microsoft WSMT table definition on FIXED_COMM_BUFFERS
requirement.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock
or semaphore is suggested to be present within a cache line. If the processors
are based on Intel NetBurst microarchitecture, two cache lines are suggested.
This could minimize the bus traffic required to service locks.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Current AcquireSpinLock() will check if timeout happens when PcdSpinLockTimeout
is not zero, even though the spin lock is already released. It may do
unnecessary operation to read timer's counter. This update is trying to acquire
spin lock firstly. If it could be acquired successfully, needn't to check
timeout at all.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This is a small convenience function that eases signaling an event group
(identified by GUID). An example where it can be used is Platform BDS
signaling the End-of-DXE event group.
The naming follows EfiNamedEventSignal().
The patch modifies the library class header, and updates the most commonly
used library instance at once. Other library instances in the edk2 tree
will be adapted in the following patches.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The InternalEmptyFunction() is currently only used by code in
"UefiNotTiano.c" -- "Library functions that abstract areas of conflict
between framework and UEFI 2.0.". In the next patches,
InternalEmptyFunction() will be used from "UefiLib.c" as well, hence
promote it to "general utility" status: move the function definition to
"UefiLib.c", and place the function declaration (which is already extern)
into "UefiLibInternal.h".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The AArch64 DAIF bits are different for reading (mrs) versus writing (msr).
The bitmask definitions assumed they were the same causing incorrect
results when trying to determine the current interrupt state through
GetInterruptState.
The logic for interpreting the DAIF read data using the csel instruction
was also incorrect and is fixed.
Replaced the magic numbers in DisableInterrupts.S and EnableInterrupts.S
with definitions for the DAIF write (daifset/daifclr) IRQ field.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
The runtime test whether the compiler supports arithmetic shift of
negative signed numbers currently relies on undefined behavior in C,
which means that all bets are off regarding whether the condition
that follows passes or fails, regardless of whether the compiler in
fact supports arithmetic shift or not.
Relevant quote from ISO C99 (6.5.7/4)
The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated bits
are filled with zeros. If E1 has an unsigned type, the value of the result
is E1 × 2^E2, reduced modulo one more than the maximum value representable
in the result type. If E1 has a signed type and nonnegative value, and
E1 × 2^E2 is representable in the result type, then that is the resulting
value; otherwise, the behavior is undefined.
For historic purposes, let's keep the test in place (although it is doubtful
we actually need it) but rewrite it in a way that prevents compilers from
this century from doing whacky things with it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19580 6f19259b-4bc3-4df7-8a09-765794883524
Raise the Tpl of async SCSI I/O callback function to TPL_NOTIFY to match
the behavior in ScsiDiskDxe driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19453 6f19259b-4bc3-4df7-8a09-765794883524
The ScsiExecuteSCSICommand() function in ScsiBusDxe driver will not signal
the event passed from UefiScsiLib when error occurs.
In this case, UefiScsiLib should close the event passing to
ScsiExecuteSCSICommand().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19448 6f19259b-4bc3-4df7-8a09-765794883524
The EBC instruction set supports memory and MMIO access, but not
I/O port access. Add EBC support to BaseIoLibIntrinsic that
generates an ASSERT() if the IoReadXX()/IoWriteXX() APIs are used.
This matches the implementation for other CPU types that do not
support I/O port access.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19234 6f19259b-4bc3-4df7-8a09-765794883524
Four new functions are added to UefiScsiLib:
ScsiRead10CommandEx
ScsiWrite10CommandEx
ScsiRead16CommandEx
ScsiWrite16CommandEx
They support both blocking and non-blocking SCSI Read/Write operation
depending on the optional parameter 'Event' passed to those APIs.
When 'Event' is NULL, these four functions will call the non-EX version
couterparts to execute blocking SCSI I/O. When 'Event' is not NULL,
non-blocking I/O operation is executed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19214 6f19259b-4bc3-4df7-8a09-765794883524
If the assert happens in a library, then it's hard to determine which
module using that library is generating that assert. Use gEfiCallerBaseName
in DebugAssert to display the module name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19127 6f19259b-4bc3-4df7-8a09-765794883524
The extended interfaces GetControl/SetControl/SetAttributes are from
EmbeddedPkg/Include/Library/SerialPortExtLib.h.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18963 6f19259b-4bc3-4df7-8a09-765794883524
The "read" word in SerialPortWrite() header comment block should be
"write".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18908 6f19259b-4bc3-4df7-8a09-765794883524
The BasePostCodeLibPort80 instance just prints UINT8 to IoPort 80. Some boards
may support 16bit or 32bit. To support them, new PCD PcdPort80DataWidth is
introduced to specify the width of data bits to Port80.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18765 6f19259b-4bc3-4df7-8a09-765794883524
Fix the wrong return value of both InternalSyncIncrement()
and InternalSyncDecrement(). The return value shouldn't
be the address of input parameter. It should be the updated
value of input parameter instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18685 6f19259b-4bc3-4df7-8a09-765794883524
As the title, this patch is to add back the useful information.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18660 6f19259b-4bc3-4df7-8a09-765794883524
Advance the *FixupData pointer after use in the second relocation pass
for runtime when handling ARM MOVW/MOVT immediate relocations.
Note that using FixupData is somewhat pointless for relocations targeting
instructions rather than data items, since the program cannot typically
modify its own instructions, and the second pass should be performed
unconditionally. But let's just fix it for now.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18597 6f19259b-4bc3-4df7-8a09-765794883524
When the local APIC is not configurated properly, function
InternalX86GetInitTimerCount() may return zero, which will lead to a
divide by zero exception in SecPeiDxeTimerLibCpu.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18593 6f19259b-4bc3-4df7-8a09-765794883524
Jordan Justen
Qiu Shumin
Star Zeng
Jiewen Yao
Zenith432
Michael Zimmermann
Jeff Fan
Feng Tian
Laszlo Ersek
Cohen, Eugene
Ruiyu Ni
Ard Biesheuvel
Hao Wu
Liming Gao
Michael Kinney
Baraneedharan Anbazhagan
Andrew Fish
Haojian Zhuang
Shia Cinnamon