Commit Graph

14 Commits

Author SHA1 Message Date
Heyi Guo 41f890164b ArmPkg/Mmu: Fix literal number left shift bug
There is a hidden bug for below code:

(1 << BaseAddressAlignment) & *BlockEntrySize

From disassembly code, we can see the literal number 1 will be treated
as INT32 by compiler by default, and we'll get 0xFFFFFFFF80000000 when
BaseAddressAlignment is equal to 31. So we will always get 31 when
alignment is larger than 31.

    if ((1 << BaseAddressAlignment) & *BlockEntrySize) {
5224: f9404be0  ldr x0, [sp,#144]
5228: 2a0003e1  mov w1, w0
522c: 52800020  mov w0, #0x1                    // #1
5230: 1ac12000  lsl w0, w0, w1
5234: 93407c01  sxtw  x1, w0

The bug can be replayed on QEMU AARCH64; by adding some debug print,
we can see lots of level 1 tables created (for block of 1GB) even
when the region is large enough to use 512GB block size.

Use LowBitSet64() in BaseLib instead to fix the bug.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18423 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:33 +00:00
Heyi Guo 946067bfb0 ArmPkg/Mmu: Fix page level calculation bug
The bug can be triggered when alignment of Base is larger than Length
by 2 level of page granularity, e.g.

Base is 0x4000_0000, Length is 0x1000

The original code will change 2MB page level and we will get a
negative remaining length.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18422 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:22 +00:00
Heyi Guo 7d189f99d8 ArmPkg/Mmu: Fix bug of aligning new allocated page table
The code has a simple bug on calculating aligned page table address.
We can just use AllocateAlignedPages in MemoryAllocationLib instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18421 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:13 +00:00
Olivier Martin ebb9235329 ArmPkg/ArmLib/AArch64: Initialize the new N+1-level page table before registering it
Prior to this change, when a new page table was created at level N+1,
the reference to the table was added to the level N translation table,
before being initialized.
It means if virtual addresses were in the address range defined by
this new table the CPU would crash as the address range was not
initialized.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16206 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10 11:25:04 +00:00
Olivier Martin 1eb5b4f28b ArmPkg/ArmLib: Set again TCR after getting the Translation Table attributes
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15837 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:36:36 +00:00
Olivier Martin 8bb7f03ade ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page tables
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-24 10:37:48 +00:00
Olivier Martin 19dc108b65 ArmPkg/ArmLib: Correct Error Handling in AArch64
There are several instances of asserts which do not also handle
the error condition in Release builds.
Because these functions are called in different location of the
code and their parameters might change during the execution, it
is safer to handle the error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15399 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26 19:34:32 +00:00
Leif Lindholm e6f3ed4340 ARM Packages: CRLF fixup
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 15:30:34 +00:00
Garrett Kirkendall 7017c2699d ArmPkg/ArmLib: Fix AARCH64 page table entry filling overrun
Update the LastBlockEntry return value when allocating a new page table block
and the parent page table entry is not valid.  Discovered when producing page
table entries for a memory region that spans multiple page table entries of a
parent page table block.  Not very memory space efficient because the rest of
the code could calculate a required page level that is deeper than some blocks
of the memory region might require.  Case that found the problem:
MemoryRegion->VirtualBase = 0
MemoryRegion->Length = 0x7F000000
This fix will create an un-needed level of page table for address
range 0 -> 0x40000000

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-24 13:10:54 +00:00
Olivier Martin d9680b9485 ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()
This macro return the address of the last entry of a translation table.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:36:16 +00:00
Olivier Martin e21227c627 ArmPkg/Library: AArch64 MMU EL1 support
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26 17:13:08 +00:00
Olivier Martin 6ea162c214 ArmPkg/ArmLib/AArch64: Use the appropriate macros and update comments
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14506 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26 17:10:51 +00:00
Olivier Martin 383070d333 ArmPkg/ArmLib/AArch64: Fixed the calculation of the last entry in the Translation Table
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14500 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24 11:50:31 +00:00
Harry Liebel 25402f5d06 ArmPkg: Added Aarch64 support
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18 18:07:46 +00:00