There are several instances of asserts which do not also handle
the error condition in Release builds.
Because these functions are called in different location of the
code and their parameters might change during the execution, it
is safer to handle the error.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15399 6f19259b-4bc3-4df7-8a09-765794883524
The function ArmReadMidr has been recently added, but that functionality was
already present under other names such as Cp15IdCode and ArmMainIdCode. This
change removes redundant code and moves the function to the Common library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
Several assembler macros use a loop at the label "dead" to trap an error.
This is difficult to debug as there is no indication of how one arrived at the loop.
This change replaces dead with distinct loops locally in the macro,
which means the cause of the hang is detectable to the debugger.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
Update the LastBlockEntry return value when allocating a new page table block
and the parent page table entry is not valid. Discovered when producing page
table entries for a memory region that spans multiple page table entries of a
parent page table block. Not very memory space efficient because the rest of
the code could calculate a required page level that is deeper than some blocks
of the memory region might require. Case that found the problem:
MemoryRegion->VirtualBase = 0
MemoryRegion->Length = 0x7F000000
This fix will create an un-needed level of page table for address
range 0 -> 0x40000000
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations
where the cache level field is at the BIT1 position.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
This macro return the address of the last entry of a translation table.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only
be invoked from EL2.
The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates
the TLBs of the current VMID.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
Olivier Martin
Leif Lindholm
Garrett Kirkendall
Harry Liebel