Commit Graph

442 Commits

Author SHA1 Message Date
Ard Biesheuvel 2cde2696f5 ArmLib/ArmV7Mmu: use 64-bit type for mapping region size
The way the v7 MMU code is invoked by the Xen port is somewhat of
a pathological case, since it describes its physical memory space
using a single cacheable region that covers the entire addressable
range. When clipping this region to the part that is 1:1 addressable,
we end up with a region of exactly 4 GB in size, which just exceeds
the range of the UINT32 variable we use in FillTranslationTable() to
track our progress while populating the page tables. So promote it
to UINT64 instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18930 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-24 07:48:06 +00:00
Heyi Guo e266db592b ArmPkg: Invalidate cache after allocating UC memory
It is implied that the memory returned from UncachedMemoryAllocationLib
should have cache invalidated. So we invalidate memory range after
changing memory attribute to uncached.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18920 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-23 07:48:33 +00:00
Leif Lindholm 3b1495156a ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias
In ArmLib, there exists an alias for ArmDataSynchronizationBarrier,
named after one of several names for the pre-ARMv6 cp15 operation that
was formalised into the Data Synchronization Barrier in ARMv6.

This alias is also the one called from within ArmLib, in preference of
the correct name. Through the power of code reuse, this name slipped
into the AArch64 variant as well.

Expunge it from the codebase.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-20 13:14:59 +00:00
Mark Rutland d855b261d1 ArmPkg/ArmPlatformPkg: position vectors relative to base
We currently rely on .align directives to ensure that each exception
vector entry is the appropriate offset from the vector base address.

This is slightly fragile, as were an entry to become too large (greater
than 32 A64 instructions), all following entries would be silently
shifted until they meet the next alignment boundary. Thus we might
execute the wrong code in response to an exception.

To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org
directives to position each entry at the precise required offset from
the base of a vector. A vector entry which is too large will trigger a
build failure rather than a runtime failure which is difficult to debug.

For consistency, the base and end of each vector is similarly annotated,
with VECTOR_BASE and VECTOR_END, which provide the necessary alignment
and symbol exports. The now redundant directives and labels are removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-19 14:39:48 +00:00
Mark Rutland fafb7e9c11 ArmPkg: correct TTBR1_EL1 settings in TCR_EL1
As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure
it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since
reset.

Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU
may make page table walks via TTBR1_EL1 at any time, potentially using
UNKNOWN values. This can result in a number of potential problems (e.g.
the CPU may load from MMIO registers as part of a page table walk).

Additionally, in the presence of Cortex-A57 erratum #822227, we must
program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value
of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a
hypervisor which makes use of PAR_EL1.

This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above
to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any
CPU capable of running EDK2 must support this granule, and given
TCR_EL1.EPD1, programming the field is not detrimental in the absence of
the erratum.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-19 14:14:25 +00:00
Ard Biesheuvel 55df704dd2 ArmPkg/ArmV7Mmu: handle memory regions over 4 GB correctly
The ARM_MEMORY_REGION_DESCRIPTOR array provided by the platform may
contain entries that extend beyond the 4 GB boundary, above which
we can't map anything on 32-bit ARM. If this is the case, map only
the 1:1 addressable part.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18900 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 16:18:40 +00:00
Ard Biesheuvel 72143137f4 ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBR
Bits 0 and 6 of the TTBRx system registers have different meanings
depending on whether a system implements the Multiprocessing
Extensions. So use separate memory attribute definitions for MP and
non-MP.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:59 +00:00
Ard Biesheuvel 65ceda9173 ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareable
Even though mapping normal memory (inner) shareable is usually the
correct choice on coherent systems, it may be desirable in some cases
to use non-shareable mappings for normal memory, e.g., when hardware
managed coherency is not required and the memory system is not fully
configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride
that makes cacheable mappings of normal memory non-shareable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18897 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:22 +00:00
Ard Biesheuvel 07070ecc76 ArmPkg/ArmV7Mmu: make cached translation table accesses shareable
To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:04 +00:00
Ard Biesheuvel 2ea66ed9f9 ArmPkg/ArmV7Lib: add function to test for presence of MP extensions
Some MMU manipulation is dependent on the presence of the multiprocessing
extensions. So add a function that returns this information.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18895 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:58:46 +00:00
Ard Biesheuvel 63dbd62964 ArmPkg/ArmV7Lib: add support for reading the ID_MMFR0 system register
Implement an accessor function for the ID_MMFR0 system register, which
contains information about the VMSA implementation. We will need this
to access the number of shareability levels and the nature of their
implementations.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18894 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:58:26 +00:00
Ard Biesheuvel a6ec831c10 ArmPkg/ArmV7Mmu: fix write-through translation table accesses
The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since
a) its meaning is unclear in the context of TTBRx, since write through
   always implies Read-Allocate and no Write-Allocate
b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC

So instead, rename it to TTBR_WRITE_THROUGH and update the definition
to reflect the name.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:58:03 +00:00
Ard Biesheuvel 6bc35cbaca ArmPkg/Mmu: set required XN attributes for device mappings
To prevent speculative intruction fetches from MMIO ranges that may
have side effects on reads, the architecture requires device mappings
to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and
EL1&0 translation regimes, respectively.)

Note that, in the ARM case, this involves moving all accesses to a
client domain since permission attributes like XN are ignored from
a manager domain. The use of a client domain is actually mandated
explicitly by the UEFI spec.

Reported-by: Heyi Guo <heyi.guo@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 11:51:06 +00:00
Ard Biesheuvel dd7a987dac ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()
The function GcdAttributeToArmAttribute() is not used anywhere in the
code base, and is only defined for AARCH64 and not for ARM. It also
fails to set the bits for shareability and non-executability that we
require for correct operation. So remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18888 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 11:50:12 +00:00
Mark Rutland 386cdfbecb ArmPkg: ensure DebugAgentVectorTable is 2K-aligned
We force alignment to 2K after generating the DebugAgentVectorTable
symbol, and hence DebugAgentVectorTable itself may not be 2K-aligned,
and table entries may not be at the correct offset from the
DebugAgentVectorTable base address.

Fix this by forcing alignment before generating the
DebugAgentVectorTable symbol.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18865 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17 13:58:19 +00:00
Ard Biesheuvel 0c9a522f28 ArmPkg/ArmLib: mark all cached mappings as (inner) shareable
Mark all cached memory mappings as shareable (or inner shareable on
AArch64) so that our view of memory is kept coherent by the hardware.

This is relevant for things like coherent DMA and virtualization (where
a guest may migrate to another core) but in general, since UEFI on ARM
is mostly used in a context where the secure firmware and possibly a
secure OS are already up and running, it is best to refrain from using
any non-shareable mappings.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-12 11:40:57 +00:00
Ard Biesheuvel 07c707858d ArmPkg/ArmDmaLib: use the cache writeback granularity for alignment
When allocating memory to perform non-coherent DMA, use the cache
writeback granule rather than the data cache linesize for alignment.
This prevents the explicit cache maintenance from corrupting
unrelated adjacent data if the cache writeback granule exceeds
the cache linesize.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18759 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:28:33 +00:00
Ard Biesheuvel c653fc2a91 ArmPkg/ArmLib: add accessor function for Cache Writeback Granule
Add a function to ArmLib that provides access to the Cache Writeback
Granule (CWG) field in CTR_EL0. This information is required when
performing non-coherent DMA.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18758 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:28:17 +00:00
Ard Biesheuvel f977e6500a ArmCacheMaintenanceLib: disallow whole D-cache maintenance operations
The ARM architecture provides no reliable way to clean or invalidate
the entire data cache at runtime. The reason is that such maintenance
requires the use of set/way maintenance operations, which are suitable
only for the kind of maintenance that is carried out when the cache is
taken offline entirely.

So ASSERT () when any of the CacheMaintenanceLib whole data cache routines
are invoked rather than pretending we can do anything meaningful here.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18756 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:27:36 +00:00
Ard Biesheuvel c722289324 ArmPkg/ArmLib: move cache maintenance sync barriers out of loop
There is no need to issue a full data synchronization barrier and an
instruction synchronization barrier after each and every set/way or
MVA cache maintenance operation. For the set/way case, we can simply
remove them, since the set/way outer loop already issues the required
barriers after completing its traversal over all the cache levels.

For the MVA case, move the data synchronization barrier out of the
loop, and add the instruction synchronization barrier to the I-cache
invalidation by MVA routine.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18755 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:27:15 +00:00
Ard Biesheuvel fbf658ebc8 ArmPkg/ArmLib: retrieve cache line length from CTR not CCSIDR
The stride used by the cache maintenance by MVA instructions should
be retrieved from CTR_EL0.DminLine and CTR_EL0.IminLine, whose values
reflect the actual geometry of the caches. Using CCSIDR for this purpose
violates the architecture.

Also, move the line length accessors to common code, since there is no
need to keep them separate between ARMv7 and AArch64.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18754 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:26:52 +00:00
Ard Biesheuvel f97ab1bbf4 ArmPkg/ArmLib: remove CCSIDR based cache info routines
The ARM architecture does not allow the actual geometries of the caches
to be inferred from the CCSIDR cache info system register, since the
geometry it reports is intended for performing cache maintenance by
set/way and nothing else. Since the ArmLib cache info routines are
based solely on CCSIDR contents, they should not be used.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:26:32 +00:00
Ard Biesheuvel acdb6dc8b7 ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()
The function ArmCleanDataCacheToPoU() has no users, and its purpose
is unclear, since it uses cache maintenance by set/way to perform
the clean to PoU, which is a dubious practice to begin with. So
remove the declaration and all definitions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:26:11 +00:00
Ard Biesheuvel cf93a37859 ArmPkg BeagleBoardPkg Omap35xxPkg: fix typo 'ArmDataSyncronizationBarrier'
Replace all instances of ArmDataSyncronizationBarrier with
ArmDataSynchronizationBarrier.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18751 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:25:50 +00:00
Ard Biesheuvel 417165735e ArmPkg/ArmLib: remove unused ARM9 support
The ARM9 ArmLib implementation is not referenced anywhere in the
tree, and unlikely to be useful going forward, considering that
ARM9 outdates even ARMv6. So remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18750 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:25:31 +00:00
Mark Rutland ee95f9e1fa ArmPkg/ArmLib: fix barriers in AArch64 ArmEnableMmu
The ARM architecture requires a DSB to complete TLB maintenance, with a
subsequent ISB being required to synchronize subsequent items in the
current instruction stream against the completed TLB maintenance.

The ArmEnableMmu function is currently missing the DSB, and hence the
TLB maintenance is not guaranteed to have completed at the point the MMU
is enabled. This may result in unpredictable behaviour.

The DSB subsequent to the write to SCTLR_EL1 is unnecessary; the ISB
alone is sufficient to complete all prior instructions and to
synchronise the new context with any subsequent instructions.

This patch adds missing DSBs to complete TLB maintenance, and removes
the unnecessary trailing DSB.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18749 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:25:12 +00:00
Ashutosh Singh f3e88737f7 ArmPkg/BdsLib: Increase fallback tftp buffer size
When performing a tftp download from a server which does not support
rfc2349 transfer size option (such as netkit-tftpd), the existing code
falls back to allocating an 8MB buffer. Since this is insufficient for
an uncompressed AArch64 Linux kernel image, double the size to 16MB.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ashutosh Singh <ashutosh.singh@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18748 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09 13:13:37 +00:00
Ard Biesheuvel 4d9a4f62cf ArmPkg/ArmLib MMU: add functions to set/clear RO and XN bits on regions
Use the refactored UpdateRegionMapping () to traverse the translation
tables, splitting block entries along the way if required, and apply
a mask + or on each to set or clear the PXN/UXN/XN or RO bits.

For now, the 32-bit ARM versions remain unimplemented.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18587 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-08 18:52:16 +00:00
Ard Biesheuvel 5ab77c6630 ArmPkg/AArch64Mmu: move page table traversal code to separate function
Move the page table traversal and splitting logic to a separate function
UpdateRegionMapping() and refactor it slightly so we can reuse it later to
implement non-executable regions, for the stack. This primarly involves
adding a value/mask pair to the function prototype that allows us to flip
arbitrary bits on each block entry as the page tables are traversed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18586 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-08 18:52:06 +00:00
Ard Biesheuvel 2afeabd1a9 ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXN
The non-privileged execute never (UXN) page table bit defined for the
EL1&0 translation regime and the execute never (XN) bit defined for the
EL2 and EL3 translation regimes happen to share the same bit position,
but they are in fact defined distinctly by the architecture. So define
both bits explicitly, and add comments in places where we take advantage
of the fact that they share the same bit position.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18585 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-08 18:51:56 +00:00
Ard Biesheuvel 9d636f57f4 ArmPkg/AArch64Mmu: remove cache maintenance for page tables
All our page tables are allocated from memory whose cacheability
attributes are inherited by the cacheability bits in the MMU control
register, so there is no need for explicit cache maintenance after
updating the page tables. And even if there were, Set/Way operations
are not appropriate anyway for ensuring that these changes make it to
main memory. So just remove the explicit cache maintenance completely.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18570 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-06 12:51:07 +00:00
Ard Biesheuvel 54d8d4dc97 ArmPkg/Mmu: do not configure block translations at level 0
Now that the AArch64 MMU code correctly identifies and handles
naturally aligned regions of more than 2 MB in size, it will happily
try to use block mappings at level 0 to map huge memory regions, such
as the single cacheable 1:1 mapping we use for Xen domU to map the
entire PA space. However, block mappings are not supported at level 0
so the resulting translation tables will be incorrect, causing
execution to fail as soon as the MMU is enabled.

So use level 1 as the minimum level at which to perform block
translations.

Reported-by: Julien Grall <julien.grall@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-02 14:48:21 +00:00
Heyi Guo 8483681426 ArmPkg/Mmu: Fix potential page table memory leak
During page entry attribute update, if there are table entries
between starting BlockEntry and LastBlockEntry, table entries will be
set as block entries and the allocated memory of the tables will be
leaked.

So instead, we break the inner loop when we find a table entry and run
outer loop again to step into the table by the same logic.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>

[ardb: move termination condition check inside the loop]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18425 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:50 +00:00
Heyi Guo edff645fe4 ArmPkg/Mmu: Increase PageLevel when table found at the targeted level
Below code has bug since *BlockEntrySize and *TableLevel are not
updated accordingly:

if (IndexLevel == PageLevel) {
  // And get the appropriate BlockEntry at the next level
  BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, \
      IndexLevel + 1, RegionStart);

  // Set the last block for this new table
  *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, \
      TT_ENTRY_COUNT);
}

Also it doesn't check recursively to get the last level, e.g. the
initial PageLevel is 1 and we already have level 2 and 3 tables at
this address.

What's more, *LastBlockEntry was not updated when we get a table and
IndexLevel != PageLevel.

So we reorganize the sequence, only updating TranslationTable,
PageLevel and BlockEntry in the loop, and setting the other output
parameters with the final PageLevel before returning.

And LastBlockEntry is only an OUT parameter.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18424 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:41 +00:00
Heyi Guo 41f890164b ArmPkg/Mmu: Fix literal number left shift bug
There is a hidden bug for below code:

(1 << BaseAddressAlignment) & *BlockEntrySize

From disassembly code, we can see the literal number 1 will be treated
as INT32 by compiler by default, and we'll get 0xFFFFFFFF80000000 when
BaseAddressAlignment is equal to 31. So we will always get 31 when
alignment is larger than 31.

    if ((1 << BaseAddressAlignment) & *BlockEntrySize) {
5224: f9404be0  ldr x0, [sp,#144]
5228: 2a0003e1  mov w1, w0
522c: 52800020  mov w0, #0x1                    // #1
5230: 1ac12000  lsl w0, w0, w1
5234: 93407c01  sxtw  x1, w0

The bug can be replayed on QEMU AARCH64; by adding some debug print,
we can see lots of level 1 tables created (for block of 1GB) even
when the region is large enough to use 512GB block size.

Use LowBitSet64() in BaseLib instead to fix the bug.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18423 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:33 +00:00
Heyi Guo 946067bfb0 ArmPkg/Mmu: Fix page level calculation bug
The bug can be triggered when alignment of Base is larger than Length
by 2 level of page granularity, e.g.

Base is 0x4000_0000, Length is 0x1000

The original code will change 2MB page level and we will get a
negative remaining length.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18422 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:22 +00:00
Heyi Guo 7d189f99d8 ArmPkg/Mmu: Fix bug of aligning new allocated page table
The code has a simple bug on calculating aligned page table address.
We can just use AllocateAlignedPages in MemoryAllocationLib instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18421 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-09 13:37:13 +00:00
Heyi Guo da70563092 ArmPkg: Bug fix for UncachedMemoryAllocationLib
NewNode is the node we found, while Node is the last node in the
list. Also update mFreedBufferSize.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18390 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-02 16:29:31 +00:00
Ard Biesheuvel 70119d2741 ArmPkg: remove ARMv6 support code
No platforms use the ARMv6 (ARM11) support code anymore. In fact, the
only reference to it in ArmPkg.dsc was commented out by Andrew in SVN
r11298 (2011-02-03) so it may well be broken. So remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18237 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-19 10:51:59 +00:00
Ard Biesheuvel f94522c823 ArmPkg: cache detected revision in ArmGicArchLib
Instead of inferring the GIC revision from the CPU id registers
and the presence/availability of the system register interface
upon each invocation, move the logic to a constructor and cache
the result.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18100 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:45:10 +00:00
Ard Biesheuvel e9e9c7e8a4 ArmPkg: copy ArmGicArchLib to ArmGicArchSecLib
Clone ArmGicArchLib into a SEC phase specific ArmGicArchSecLib
so that we can modify the former in a subsequent patch to cache
the GIC revision in a global variable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18099 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:44:58 +00:00
Ard Biesheuvel 8d13298b80 ArmPkg: split off ArmGicArchLib from ArmGicLib
The current implementation of ArmGicGetSupportedArchRevision ()
that is used by all ARM platforms is entirely stateless (in order
to support being executed from flash) so it needs to interrogate
the hardware for the supported GIC revision upon each invocation.

However, this statelessness is only needed for SEC type modules;
in all other cases, we could easily determine the GIC revision once,
and store the result in a global variable.

In preparation of having separate early and normal versions, this patch
introduces the ArmGicArchLib library class and default implementation,
and moves the existing ArmGicGetSupportedArchRevision () into it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:44:44 +00:00
Olivier Martin c75d3eb6be ArmPkg/BdsLib: Remove Linux loader from BdsLib
This change removes the embedded Linux Loder from BdsLib.
BdsLib becomes OS agnostic.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17969 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-14 14:35:20 +00:00
Olivier Martin 0c72676d37 ArmPkg/BdsLib: Replaced BdsLoadApplication() by LocateEfiApplicationInFv()
Replaced the function BdsLoadApplication() by two explicit
functions that load the EFI application either by its GUID
or its Name.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17966 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-14 14:30:08 +00:00
Olivier Martin 4d95a9aa08 ArmPkg/ArmLib: Fixed build after recent BaseTools changes
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17631 6f19259b-4bc3-4df7-8a09-765794883524
2015-06-15 15:31:29 +00:00
Olivier Martin 9d8ee7815c ArmPkg/BdsLib: Fixed TFTP when there are directories in the name
The TFTP Device Path might contain a list of File Path device
path nodes.
ConvertDevicePathToText() allows to concatenate these File Path
nodes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17539 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-29 14:00:39 +00:00
Olivier Martin 7fbd1eb231 Renamed ArmPlatformPkg/ArmVirtualizationPkg into ArmVirtPkg
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17537 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-29 13:50:43 +00:00
Heyi Guo c37e542ba0 ArmPkg: fix ArmWriteCntkCtl simple code bug
We need to use msr instruction to write system register. It seems the
code was simply copied from ArmReadCntkCtl.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17440 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-13 18:21:58 +00:00
Olivier Martin b398eada16 ArmPkg/BdsLib: Fixed line ending
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17438 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-13 18:19:51 +00:00
Ard Biesheuvel 459823d9b2 ArmPkg: update BdsLib to updated definition of EFI_LOAD_OPTION
Since there is now a formal definition of EFI_LOAD_OPTION, we can no
longer typedef it as a UINT8*. So update the code to use the common
definition, which is not a pointer type, hence the additional changes
to the C code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17410 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-11 17:37:24 +00:00
Ard Biesheuvel ffaa6b46ef ArmPkg: fix pointer indirection bug in BdsFirmwareVolumeLoadImage()
The EFI_FIRMWARE_VOLUME2_PROTOCOL::EFI_FV_READ_SECTION prototype
takes a pointer to a pointer to an output buffer, so we should
not dereference Image (which is a pointer to pointer type itself)
but pass its value directly.

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17357 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-07 15:37:10 +00:00
Olivier Martin cc053ee6da ArmPkg/BdsLib: Exposed ShutdownUefiBootServices() in the BdsLib interface
Other libraries/modules could use it (eg: EFI Shell command `runaxf`).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17297 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05 14:58:57 +00:00
Ard Biesheuvel 6ea34e3a45 ArmPkg: remove cache maintenance by VA operation range size threshold
This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.

Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.

To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-14 11:54:40 +00:00
Olivier Martin 80d3139724 ArmPkg/BaseMemoryLib(Sym|Vstm): Do not post increment returned pointer
InternalMemScanMem(8|16|32|64) was returning a pointer that was
post incremented from the expected returned value.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <ronald.cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17108 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-02 13:51:28 +00:00
Laszlo Ersek 1fce963d89 ArmPkg: DebugPeCoffExtraActionLib: debugger commands are not errors
PeCoffLoaderRelocateImageExtraAction() prints helpful debugger commands
for source level debugging. These messages should not be printed on the
EFI_D_ERROR level; they don't report errors. Change the debug level
(bitmask, actually) to EFI_D_LOAD | EFI_D_INFO, because the messages are
printed in relation to image loading, and they are informative.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@arm.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16983 6f19259b-4bc3-4df7-8a09-765794883524
2015-03-02 16:19:26 +00:00
Ronald Cron 6332ffb0af ArmPlatformPkg/Bds: Remove any use of the "Fdt" UEFI variable
Remove the option to update the "Fdt" UEFI variable in the ARM BDS as
the "setfdt" EFI Shell command provides this service from now.

Remove the use of this variable in the legacy kernel boot loader and
use the FDT installed in the configuration table instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16940 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-26 11:02:39 +00:00
Olivier Martin df320b1084 ArmPkg/BdsLib: Added support to change the given DevicePath of a Boot Entry
Some boot entries might not have a EFI Device Path FilePath
attached to it (eg: EFI device Path for removable device path).
This patch allows a support loader to edit the EFI Device Path
and for instance add \EFI\BOOT\BOOT(ARM|AA64).EFI

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16930 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25 19:04:59 +00:00
Laszlo Ersek 16b7aff06b ArmPkg: ArmArchTimerLib: conditionally rebase to actual timer frequency
Allow a platform to set PcdArmArchTimerFreqInHz to zero, and consider it a
request to use the actual timer frequency.

No global variable is introduced, so that the library can be used in PEIMs
that execute from flash.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16691 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02 12:01:48 +00:00
Laszlo Ersek b36bc5af58 ArmPkg: ArmArchTimerLib: use edk2-conformant (UINT64 * UINT32) / UINT32
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16690 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02 12:01:38 +00:00
Laszlo Ersek 074a67fc80 ArmPkg: ArmArchTimerLib: clean up comments
In the next patch we'll slightly reorganize TimerConstructor(). Let's
improve the comments first.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16689 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02 12:01:29 +00:00
Ronald Cron ad7e31b505 ArmPkg/BdsLib: Close file after reading an Image
When loading an image from a file, close the file after reading from it.
Use OpenProtocol instead of HandleProtocol to retrieve the simple file
system protocol interface.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16586 6f19259b-4bc3-4df7-8a09-765794883524
2015-01-06 15:51:02 +00:00
Ronald Cron f88a751a07 ArmPkg/BdsLib: Fix DHCP4 configuration
Fix DHCP4 configuration as part of TFTP boot process to get the IP address of
the gateway and the subnet mask from the DHCP server.
Fix a memory leak when the download from the TFTP server fails as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16582 6f19259b-4bc3-4df7-8a09-765794883524
2015-01-06 15:46:36 +00:00
Olivier Martin 85774874bc ArmPkg/BdsLib: Update the size of the Device Tree before booting Linux
The memory reserved to load the device tree is over-allocated when
UEFI loads the blob to update the device tree with additional
information such as the command line, the initrd, etc.

This change ensures the total size declared by the device tree matches
the actual data (and not the over-allocated size value).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16517 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12 19:15:37 +00:00
Ronald Cron 061568e2d5 ArmPkg/BdsLib: Rework TFTP boot
Rework the downloading of an image from a TFTP server to do not
depend on any "PXE specific" setting of the DHCP server.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16516 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12 19:14:22 +00:00
Olivier Martin 4a2928934b ArmPkg/ArmArchTimerLib: Promotes 32bit value to prevent overflow
Both MicroSeconds and PcdArmArchTimerFreqInHz are 32-bit values on
AArch32 so their multiplication produces 32-bit result that might
cause wrong calculation.

Example: With MicroSeconds = 200 us, PcdArmArchTimerFreqInHz = 24MHz.
200*24000000 = 0x1_1E1A_3000 => So 0x1E1A_3000 when the type is UINT32.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16329 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11 00:52:46 +00:00
Olivier Martin 284fb5c811 ArmPkg/CompilerIntrinsicesLib: Fixed memmove() and memset()
- Fixed memmove when going backward: the copy started one byte
  after the end of the region to copy
- memset: - removed unused register
          - fixed arguments size and character arguments were
            actually reversed
- Added memmove() to ARM32 GCC

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16328 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11 00:52:11 +00:00
Olivier Martin fb7ea6114a ArmPkg: Ensured the stack is always quad-word aligned
From the AArch64 Procedure Call Standard (ARM IHI 0055B):

  5.2.2.1 Universal stack constraints
  At all times the following basic constraints must hold:
  - SP mod 16 = 0. The stack must be quad-word aligned.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11 00:51:11 +00:00
Leif Lindholm bb5420bb2b ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.
Some AArch64 platforms have RAM and flash devices >4GB.
Update some additional Pcd entries to 64-bit, and change
the corresponding PcdGet32 calls to PcdGet64.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11 00:43:03 +00:00
Olivier Martin 8dd618d211 ArmPkg/ArmLib: Removed duplicated invalidate TLB function
ArmInvalidateInstructionAndDataTlb() was doing the same thing as
ArmInvalidateTlb().
Both invalidate Data and Instruction TLBs.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27 15:38:55 +00:00
Ronald Cron 5521b5cc73 ArmPkg/SemihostLib: Add library functions
Add library functions to rename a file and get a temporary name
for a file through the semi-hosting interface.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16238 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27 10:38:18 +00:00
Ronald Cron c20f8ec661 ArmPkg/Semihostlib: Rename semi-hosting open option
Change mnemonic SEMIHOST_FILE_MODE_CREATE with mnemonic SEMIHOST_FILE_MODE_UPDATE.
The bit referred to by this mnemonic is for the semi-hosting open mode code the
equivalent of the + in the ISO C fopen mode terminology. This allows to select the
so called update mode for which both read and write are allowed on the open file.
The mnemonic SEMIHOST_FILE_MODE_UPDATE is more in line with the ISO C fopen mode
terminology. A description of the ISO C fopen modes can be found here :
http://pubs.opengroup.org/onlinepubs/009695399/functions/fopen.html.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16237 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27 10:37:20 +00:00
Olivier Martin ebb9235329 ArmPkg/ArmLib/AArch64: Initialize the new N+1-level page table before registering it
Prior to this change, when a new page table was created at level N+1,
the reference to the table was added to the level N translation table,
before being initialized.
It means if virtual addresses were in the address range defined by
this new table the CPU would crash as the address range was not
initialized.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16206 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10 11:25:04 +00:00
Olivier Martin 1a70a690ea ArmPkg/UncachedMemoryAllocationLib: Track uncached memory allocations
Keeping track of uncached memory allocations prevents doing expensive
cache operations (eg: clean & invalidate) on newly allocated regions
by reusing regions where possible

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16205 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10 11:24:11 +00:00
Olivier Martin 9180ab73e6 ArmPkg/ArmPsciResetSystemLib: Made the library only using SMC
Only ArmVirtualizationPkg based platforms are expected to use
the dynamic method to choose between SMC and HVC to invoke PSCI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16204 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10 11:22:50 +00:00
Ard Biesheuvel 021da07b66 ArmPsciResetSystemLib: read PSCI method in constructor
As this library is used in the implementation of a Runtime Service,
make sure to access dynamic PCDs only in the constructor.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16108 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-16 00:51:17 +00:00
Ard Biesheuvel ca3026d361 ArmPkg: Introduced ArmPsciResetSystemLib
This implementation of EfiResetSystemLib uses ARM PSCI calls to perform
reboot and poweroff, using either HVC or SMC calls.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16089 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10 18:47:30 +00:00
Ard Biesheuvel 58e92b394e ArmPkg: Add ArmHvcLib
This is a utility library closely modeled after ArmSmcLib, that allows
hypervisor call (HVC) instructions to be issued from C code.

Change-Id: I5f5c65f83e910ff98dbb2f5b031dad8c4f663daa
Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16088 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10 18:46:23 +00:00
Ard Biesheuvel 432dc3c135 ArmPkg/ArmSmcLib: fix stack handling in .asm version of SMC wrapper
This fixes a bug in the stack handling in the RVCT .asm version
of the SMC wrapper.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16086 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10 18:44:19 +00:00
Ard Biesheuvel f8d7d6e151 ArmPkg,ArmPlatformPkg: Allow dynamic PCDs for memory base and size
This changes the definition and a bunch of references to
gArmTokenSpaceGuid.PcdSystemMemoryBase and
gArmTokenSpaceGuid.PcdSystemMemorySize so they can be declared as dynamic PCDs
by the platform. Also, move the non-SEC call to
ArmPlatformInitializeSystemMemory() earlier, so a platform has a chance to set
these PCDs before they are first referenced.

The purpose is allowing dynamically instantiated virtual machines to declare
the system memory by passing a device tree.

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16079 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:11:30 +00:00
Ard Biesheuvel 4f6d34b434 ArmPkg: Move TimerDxe and ArmArchTimerLib to new ArmGenericTimerCounterLib
Move TimerDxe and ArmArchTimerLib to ArmGenericTimerCounterLib, and update all
platforms to select the physical counter instance they have been using
implicitly all along.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16078 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:10:18 +00:00
Ard Biesheuvel bcf37cf600 ArmPkg: add ArmGenericTimerCounterLib implementation using virtual timer
This adds an implementation of ArmGenericTimerCounterLib using the virtual
architected generic timer.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16076 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:07:43 +00:00
Ard Biesheuvel cece12d3f6 ArmPkg: add ArmGenericTimerCounterLib implementation using physical timer
This adds an implementation of ArmGenericTimerCounterLib using the physical
architected generic timer.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16075 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:06:10 +00:00
Ard Biesheuvel d4bb43cee1 ArmPkg: Renamed ArmArchTimerLib.h to ArmArchTimer.h
The ArmArchTimerLib.h include file is not directly related to the TimerLib
instance ArmArchTimerLib, so the name is confusing. Rename to ArmArchTimer.h
instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16073 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:03:21 +00:00
Ard Biesheuvel dc63be2495 ArmPkg: allow dynamic GIC base addresses
Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared
as PcdsDynamic by the platform, so virtual machines can set these
properties during boot. As the PcdGet32() calls now call into the
PCD database, cache the values that are required during the handling
of interrupts.

Contributed-under: TianoCore Contribution Agreement 1.0
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16072 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 16:00:47 +00:00
Harry Liebel 01289ec36f ArmPkg/ArmDisassemblerLib: ARMThumb and AArch64 fixes
- Fix ARM Thumb mask operator. This was flagged by a toolchain as warning
  "use of logical '&&' with constant operand [-Wconstant-logical-operand]"
- AArch64 should not be building the ARM32 disassemblers.
- Add a AArch64 build target. The disassembler is still to be
  implemented.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16069 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-09 15:57:18 +00:00
Olivier Martin e754c233a1 ArmPkg/BdsLib/Arm: Check Linux image and parameters are not overlapping
Check Linux image and parameters are not overlapping with each other.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16013 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01 13:24:01 +00:00
Olivier Martin 5779aaafe9 ArmPkg/BdsLib/Arm: Clean Data cache before disabling it
It is actually the same sequence as AArch64.
Without cleaning the data cache prior to disable the cache, the LR value
pushed on the stack when entering in ArmCleanInvalidateDataCache()
might have been overwritten by this specific cache line maintenance.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16012 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01 13:21:54 +00:00
Olivier Martin 33292af5f1 ArmPkg/TimerDxe: Changed calculation to allow 1KHz granularity frequency
Prior to this change the frequency was rounded to 1Mhz.
This change rounds the timer frequency to 1KHz.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15921 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-27 10:12:00 +00:00
Olivier Martin d340ef7542 ArmPkg/ArmArchTimerLib: Remove non required [depex] and IoLib
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15903 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-26 10:16:16 +00:00
Ronald Cron 91c38d4e94 ARM Packages: Replace tabs by spaces for indentation
Replace tabs by spaces for indentation to comply to EDK2 coding standards.
Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf",
 "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg,
BeagleBoardPkg or Omap35xxPkg.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-26 10:14:17 +00:00
Olivier Martin 5a539eb536 ArmPkg/ArmLib/ArmV7: Fixed ArmIsMpCore()
The function was not returning the expected value.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15850 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-20 17:57:34 +00:00
Olivier Martin 1eb5b4f28b ArmPkg/ArmLib: Set again TCR after getting the Translation Table attributes
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15837 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:36:36 +00:00
Olivier Martin 04ad241e20 ArmPkg/BdsLib: Prevent a hang in BdsConnectDevicePath() when a sub-device path is not found
Some device paths were making BdsConnectDevicePath() hang.
To prevent these hangs we check if the handle returned by
gBS->LocateDevicePath() is the same after each iteration.

An example of a device path that hangs:
PciRoot(0x0)/Pci(0x1,0x0)/USB(0x0,0x0)/USB(0x3,0x0)/HD(...)
The connect controller function manages to find PciRoot()/Pci(0x1,0x0)
but the USB driver does not produce USB(0x0,0x0)/USB(0x3,0x0) and
returns EFI_SUCCESS on its initialization.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15835 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:35:14 +00:00
Ronald Cron 3402aac7d9 ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:29:52 +00:00
Ronald Cron 62d441fb17 ARM Packages: Corrected non-DOS line endings
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:22:20 +00:00
Olivier Martin b4e53e389d ArmPkg/ArmSmcLib: Fixed SMC helper functions
The SMC helper functions were buggy as they were assuming that
the values in x1-x7 registers were preserved across an SMC call,
which is not the case.  This patch fixes this issue.

It also simplifies the code by providing only 1 version of the SMC
helper function.  We used to have 4 versions depending on the number
of arguments.  The problem with this approach was that the number of
arguments also dictated the number of return values, which is
completely unrelated.  E.g. you can have an SMC call that takes
1 argument but returns 4 values.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15748 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-04 14:18:13 +00:00
Harry Liebel ef0fa8e16b ArmPkg: Remove BasePeCoffLib
ArmPkg contains unused and outdated code for runtime PE/COFF image
relocation.

- Use the version in MdePkg instead.
- Remove references to this package from BeagleBoardPkg.

ArmPkg/BasePeCoffLib was added to deal with MOVT instruction that
was not part of the PE/COFF specification at that time.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15712 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29 14:13:21 +00:00
Olivier Martin 6d0ca2577c ARM Packages: Force the SEC modules to be 2K aligned for AArch64
The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.

A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15 09:24:25 +00:00
Olivier Martin 9232ee5338 ArmPkg/BdsLib: Removed PSCI discoverability from the Linux loader
Some platforms might decide to not support PSCI in their FDT-aware Linux
system even if their firmware supports it.
It is the responsibility of the platform engineer to provide the appropriate FDT.

The PCD gArmTokenSpaceGuid.PcdArmPsciSupport is not required anymore.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15658 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15 09:21:41 +00:00
Eugene Cohen ffb91edfd5 ArmPkg/ArmLib: Improved ArmConfigureMmu Performance
Data & Instruction Caches can be kept enabled while the new
translation table is filled.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15647 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-09 11:14:36 +00:00
Olivier Martin edc93a3191 ArmPkg/BdsLib: Prevent memory leak whith TFTP
In some case, the size of the downloaded TFTP image cannot be known.
An arbitrary larger buffer is allocated to receive the image.
We need to make sure when we free the buffer we free the size
of the allocated buffer and not the size of the actual image.
 
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15609 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01 09:27:19 +00:00
Olivier Martin a6217114e3 ArmPkg/ArmCacheMaintenanceLib: Fixed comment (and coding style)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15608 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01 09:26:28 +00:00
Olivier Martin 27331bff97 ArmPkg: Added new ARM Processor Feature Register definitions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03 16:39:23 +00:00
Olivier Martin 01674afdad ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.
Cache maintenance operations by Set/Way require that the Write Buffer
be drained before the cache is flushed.  Without that, the flush can
miss the most recent values written as they are still "pipelined".
That has unfortunate consequences, especially where code is being
copied to RAM.
The fix is to add DSB instructions before the affected operations.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03 16:37:29 +00:00
Olivier Martin 451b665890 ArmPkg/DefaultExceptionHandlerLib/Aarch64: Added friendly debug message
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15549 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03 16:34:17 +00:00
Olivier Martin d8f36fb568 ArmPkg/BdsLib: Added support for TFTP servers without 'tsize' extension
Some TFTP servers do not have 'tsize' extension.
This change allows to download files from TFTP servers that do not have
this extension by trying to download the file into a pre-allocated buffer.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15539 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-19 16:41:25 +00:00
Brendan Jackman 271ce4bd70 ArmPkg/BdsLib/AArch64: Added more useful error messages when loading Linux
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15528 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14 16:41:04 +00:00
Brendan Jackman 1aaa6f61a5 ArmPkg/BdsLib: Fix allocating kernel buffer in TFTP
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15527 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14 16:39:43 +00:00
Mark Salter 10ddca8db9 ArmPkg/BdsLib: Fix booting with partial paths
Boot entries created by efibootmgr may contain a partial device path
to the EFI application to boot. These entries begin with a partition
device path whereas entries created via ARM Boot Manager contain a
full path to the EFI application. The ARM BDS code will fill in the
missing parts of this partial device path as it does for removeable
device paths. This allows the application to be loaded and started.
However, the current code passes the original partial device path to
gBS->LoadImage() and thus LoadImage is unable to find a DeviceHandle
for the path. This means the application being booted cannot find the
boot device from the Loaded Image Protocol structure. In the case of
grub, this prevents the grub config file from being found. This patch
fixes this by making sure the full path is propagated back to the
caller of gBS->LoadImage() so that a proper DeviceHandle gets passed
to the application being booted.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15518 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08 15:09:27 +00:00
Brendan Jackman 73ca50096e ARM Packages: Use AND instead of BIC instruction with immediate
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a
AND with the immediate inverted, but Clang's integrated assembler emits an
error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08 14:59:04 +00:00
Brendan Jackman 919a3a026c ARM Packages: use GCC_ASM_EXPORT to export functions
This ensures the .type directive is used to mark them as function symbols

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08 14:55:52 +00:00
Brendan Jackman 45440744c4 ArmLib/AArch64Support.S: remove export of unimplemented function
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15505 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08 14:54:46 +00:00
Brendan Jackman ef7b378605 ARM Packages: Remove GCC filter for AARCH64 assembly files
Some non-GCC toolchain might support the GNU assembly language.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08 14:54:11 +00:00
Olivier Martin 8bb7f03ade ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page tables
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-24 10:37:48 +00:00
Olivier Martin d8dc9f0af5 ArmPkg: Fixed GetEnvironmentVariable() when the UEFI Variable did not exist
The function was allocating a buffer for the read value from the UEFI Variable.
But it was returning the pointer of the default value when the variable was
not present.
It could cause error when the default value and the returned value were free
when these addresses were the same (double FreePool on the same address).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15427 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-02 17:32:29 +00:00
Olivier Martin 19dc108b65 ArmPkg/ArmLib: Correct Error Handling in AArch64
There are several instances of asserts which do not also handle
the error condition in Release builds.
Because these functions are called in different location of the
code and their parameters might change during the execution, it
is safer to handle the error.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15399 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26 19:34:32 +00:00
Olivier Martin 47d183db53 ArmPkg/ArmCortexA5x: Declared the helper functions to access the CPU Extended Control Register
This register is A5x specific. It is the reason why the code moved from ArmLib
to ArmCpuLib/ArmCortexA5xLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26 19:32:48 +00:00
Olivier Martin 52d44f77c2 ArmPkg/ArmLib: Added helper functions for accessing CPU ACTLR
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15396 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26 19:31:01 +00:00
Harry Liebel d276ac10f1 ArmPkg/SemihostFs: Various fixes for the file system
- Fix file deletion from the shell.
- Fix file creation using the shell editor.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15390 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-25 11:04:41 +00:00
Harry Liebel 228fdff4be ArmPkg/SemihostLib: Made arguments 'native' size
The arguments passed to the semi-hosing backend should
be of 'native' size to match register widths.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15389 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-25 11:03:54 +00:00
Olivier Martin 5456c26c2f ArmPkg/CompilerIntrinsicsLib: Added memset() to AArch64
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15384 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-24 15:30:48 +00:00
Olivier Martin 5ee57c2d7d ArmPkg/ArmLib: Removed unused AArch64 files
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15382 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-24 15:29:03 +00:00
Olivier Martin 647517279d ArmPkg/ArmLib: Renamed Cp15CacheInfo into ArmCacheInfo
CTR (Cache Type Register) has the same format on ARMv7 and AArch64.
Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function
architecture independent.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-24 15:26:22 +00:00
Olivier Martin d9bd3f11cb ArmPkg/ArmLib: Removed unused ArmSwitchProcessorMode & ArmProcessorMode functions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15380 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-24 15:25:44 +00:00
Olivier Martin 27995cd5d6 ArmPkg: Tidy assembler code
- Fixed typo
- Removed unreachable 'dead' loop

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 11:01:00 +00:00
Olivier Martin f6c5a29bb9 ArmPkg/ArmLib: Rationalise ArmReadMidr and cognate functions.
The function ArmReadMidr has been recently added, but that functionality was
already present under other names such as Cp15IdCode and ArmMainIdCode.  This
change removes redundant code and moves the function to the Common library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 11:00:07 +00:00
Olivier Martin 992a1f830d ArmPkg/ArmLib: Fix compilation error with -O3 switch
A warning is reported because ArmArchTimerReadReg may theoretically result
in an unititialised value.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15275 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 10:59:25 +00:00
Olivier Martin f0247796cb ArmPkg/ArmLib: ArmReadVBar implementation missing in AArch64
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15274 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 10:58:46 +00:00
Olivier Martin eaa84fd553 ArmPkg: Replace single dead loop.
Several assembler macros use a loop at the label "dead" to trap an error.
This is difficult to debug as there is no indication of how one arrived at the loop.
This change replaces dead with distinct loops locally in the macro,
which means the cause of the hang is detectable to the debugger.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 10:57:55 +00:00
Olivier Martin 0ff0e414d1 ArmPkg/ArmLib: Move common definitions from ArmV7Lib.h & AArch64Lib.h to ArmLib.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15272 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01 10:57:09 +00:00
Olivier Martin 51ad04cbd1 ARM Packages: Include 'AsmMacroIoLibV8.h' instead of the 32bit version
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15256 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24 19:20:16 +00:00
Garrett Kirkendall b83a92b34e ArmPkg/BdsLib: Support ignoring EfiReservedMemoryType when updating the FDT.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15255 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24 16:27:48 +00:00
Leif Lindholm e6f3ed4340 ARM Packages: CRLF fixup
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 15:30:34 +00:00
Olivier Martin 9401d6f4b9 ArmPkg/ArmLib: Added ArmReadMidr()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15240 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 15:14:41 +00:00
Olivier Martin 226d5572ad ArmPkg/BdsLib: Removed unused MachineType argument (AArch64)
MachineType was used on 32-bit.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15239 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 15:13:44 +00:00
Olivier Martin 4e57d6d70b ArmPkg/ArmLib: VBAR_ELx not written correctly when handler above 4GB
The function ArmWriteVBar had a UINT32 parameter.
Need to change it to UINT.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15208 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-05 12:53:09 +00:00
Garrett Kirkendall 7017c2699d ArmPkg/ArmLib: Fix AARCH64 page table entry filling overrun
Update the LastBlockEntry return value when allocating a new page table block
and the parent page table entry is not valid.  Discovered when producing page
table entries for a memory region that spans multiple page table entries of a
parent page table block.  Not very memory space efficient because the rest of
the code could calculate a required page level that is deeper than some blocks
of the memory region might require.  Case that found the problem:
MemoryRegion->VirtualBase = 0
MemoryRegion->Length = 0x7F000000
This fix will create an un-needed level of page table for address
range 0 -> 0x40000000

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-24 13:10:54 +00:00
Olivier Martin cf9530e686 ArmPkg/CompilerIntrinsicsLib: Make __aeabi_memcpy the same as memcpy
This code also removed some redundant instructions.

__aeabi_memcpy doesn't require preservation of r0 (as memcpy does),
which could save a push, but the code has been left to keep things consistent.

The reason __aeabi_memcpy has been added to the .S file is so it will be available
to toolchains that use the GCC assembler but the full ARM EABI (i.e. current LLVM)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15124 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-15 12:24:31 +00:00
Olivier Martin c357fd6a1f ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64
The System Memory region might be out of the 32-bit memory space.

This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:

-  # System Memory (2GB)
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+  # System Memory (4GB)
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000

EFI Shell and Linux kernel boot successfully.

Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>




git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-10 11:27:31 +00:00
Olivier Martin b2ce4a3961 ARM Packages: Removed 'inline' keyword
'inline' keyword is not supported by the C89 (version used by EDK2).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14957 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10 16:39:54 +00:00
Olivier Martin 377a32dbed ArmPkg/ArmDisassemblerLib: Fixed logical/bitwise operator confusion
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14955 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10 16:38:17 +00:00
Olivier Martin ff58c9147b ArmPkg/BdsLib: Fixed the alignment of the relocated Device Tree
When the Device Tree was loaded above the 32bit address space the operation:
*RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment);
was returning an incorrect address.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28 21:40:48 +00:00
Olivier Martin 893e5532be ArmPkg/DebugPeCoffExtraActionLib: Fixed the printing of the location of the EFI modules
When loaded above the 32-bit address space the address requires more than 8 characters.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28 21:39:46 +00:00
Olivier Martin 168d724568 ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLib
These functions are not chipset specific.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28 21:37:36 +00:00
Olivier Martin 433a49a094 ArmPkg/ArmLib: Revert change 'Fixed field shifting in CLIDR_EL1 (AArch64)'
The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations
where the cache level field is at the BIT1 position.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23 09:42:05 +00:00
Olivier Martin b7dbd9c27a ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16 09:33:55 +00:00
Olivier Martin db06c2d723 ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the Buffer
The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did
not return the lowest aligned address.

Example:
*DeviceAddress = 0xB000C001;
*DeviceAddress - BASE_4KB - 1 = 0xB000B000;
Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000
... while we where expected 0xB000C000.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02 13:13:29 +00:00
Roy Franz c6ba1c1285 ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02 09:10:17 +00:00
Olivier Martin 6adbd5b4d2 ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()
This helper function converts the section attributes into their page equivalents.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:37:50 +00:00
Olivier Martin d9680b9485 ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()
This macro return the address of the last entry of a translation table.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:36:16 +00:00