https://bugzilla.tianocore.org/show_bug.cgi?id=182
The function TimerDriverSetTimerPeriod() disables the HPET timer
while the HPET timer HW is reprogrammed with a new timer period.
However, the MMIO write to disable the HPET timer HW can be
delayed and an HPET timer interrupt may be processed in the middle
of reprogramming the HPET timer HW and this may produced unexpected
results.
The fix is to raise TPL to TPL_HIGH_LEVEL in
TimerDriverSetTimerPeriod() during the time the HPET timer HW is
reprogrammed. This guarantees that no timer interrupts are
processed during reprogramming.
The TimerDriverGenerateSoftInterrupt() function in this same
driver also raises TPL to TPL_HIGH_LEVEL, so this fix matches
the logic that is already used in another function for the same
reason.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Comparator register automatically grow without breaking main counter register, this allow other driver to use HPET main counter.
Timer register overflow handle.
32-bit HPET timer support.
TimerDriverSetTimerPeriod is changed to handle HPET timer interrupt delivered into real mode.
Signed-off-by: li-elvin
Reviewed-by: vanjeff
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12700 6f19259b-4bc3-4df7-8a09-765794883524
Minor update to logic to prevent writing a the read-only MSI Capability bit with 0 when HPET supports MSIs
Signed-off-by: mdkinney
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12272 6f19259b-4bc3-4df7-8a09-765794883524
Michael Kinney
Giri P Mudusuru
Tycho Nightingale
rsun3
li-elvin
mdkinney