Add HII definitions from UEFI 2.6 for HII Image Variability and PNG
Blocks
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
The UEFI2.5 Errata (Mantis ticket 1472 -
https://mantis.uefi.org/mantis/view.php?id=1472) updated
'PortMultiplierPort' parameter description for the following services in
EFI_ATA_PASS_THRU_PROTOCOL:
1. PassThru
2. BuildDevicePath
3. ResetDevice
Now, if there is no port multiplier on a ATA controller port, the
PortMultiplierPort parameter should be set to 0xFFFF instead of 0.
Please note that this is an incompatible semantic change. The consumer of
EFI_ATA_PASS_THRU_PROTOCOL needs to re-examine its usage to follow UEFI
2.5 Errata mantis 1472.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The UEFI2.5 spec (Mantis ticket 1353 -
https://mantis.uefi.org/mantis/view.php?id=1353) updated the Port
Multiplier Port Number description of SATA device path to use 0xFFFF when
the device is directly connected to the HBA.
Please note that this is an incompatible semantic change. The consumer of
SATA device path needs to re-examine its usage to follow UEFI 2.5 mantis
1353.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The ComId for Block SID authentication command is
0x0005 according to "TCG Storage Feature Set: Block
SID Authentication Specification Version 1.0.0". Update code to
follow this spec requirement.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Revert AuditMode/DeployedMode definition from Customized Secure Boot feature defined in UEFI2.5 Mantis 1263.
The feature has been moved to
https://github.com/tianocore/edk2-staging/tree/Customized-Secure-Boot
Previous check-in hash is
SHA-1: 79e7b64727
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: El-Haj-Mahmoud Samer <samer.el-haj-mahmoud@hpe.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
This patch adds more check in SmmIsBufferOutsideSmmValid(), to make sure that
SMM communication buffer is only EfiReservedMemoryType/EfiRuntimeServicesCode/
EfiRuntimeServicesData/EfiACPIMemoryNVS. So that the communication buffer will
not touch any OS memory.
The assumption is that a platform reports valid SMM communication buffer at
EndOfDxe, because EndOfDxe is last hook point that SMM code can call-out to
get memory map information.
A platform MUST finish SMM communication buffer allocation before EndOfDxe.
If a DXE or OS driver need do communication after EndOfDxe, it can either
allocate SMM communication buffer before EndOfDxe and save it, or consume
EDKII_PI_SMM_COMMUNICATION_REGION_TABLE table to get general fixed comm buffer.
This is designed to meet Microsoft WSMT table definition on FIXED_COMM_BUFFERS
requirement.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Add #defines for "Expect" header, which is a part of RFC 2616
and used for HTTP PUT/POST operations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hegde, Nagaraj P <nagaraj-p.hegde@hpe.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
In PerformanceLib, Identifier is for single PERF, not the pair of PERF.
When find the matched START and END pair, the identifier will not be checked.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock
or semaphore is suggested to be present within a cache line. If the processors
are based on Intel NetBurst microarchitecture, two cache lines are suggested.
This could minimize the bus traffic required to service locks.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Current AcquireSpinLock() will check if timeout happens when PcdSpinLockTimeout
is not zero, even though the spin lock is already released. It may do
unnecessary operation to read timer's counter. This update is trying to acquire
spin lock firstly. If it could be acquired successfully, needn't to check
timeout at all.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The Microsoft Debug Port Table 2 (DBG2) specification revision
October 6, 2015 adds support for Serial Port Subtypes for ARM.
This patch adds these definitions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The Serial Port Console Redirection Table specification Version 1.03 -
August 10, 2015 adds support for Serial Port Subtypes for ARM. These
Subtypes are described in the Table 3 of the Microsoft Debug Port Table
2 (DBG2) Specification - December 10, 2015.
This patch adds macro definitions for these.
Code at: 79678a0f39
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
These definitions are defined in SD physical layer simplified spec
and eMMC electrical standard spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
The definitions are defined in TCG storage core and opal spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
PcdUartDefaultReceiveFifoDepth is added to indicate UART default
receive FIFO depth.
Type of UINT16 is enough for FIFO depth.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
As the SMBIOS table types belong to the SMBIOS standard, they were
moved from the SMBIOS Protocol header into the SMBIOS
IndustryStandard header without the EFI_-prefix. Defines with the
EFI_-prefix have been kept in the Protocol header for
backwards-compatibility, resolving to the IndustryStandard defines.
The same has been done with the C types.
The SMBIOS table header structure had been duplicated -
SMBIOS_STRUCTURE in the IndustryStandard header and
EFI_SMBIOS_TABLE_HEADER in the Protocol file - and thus the
Protocol type was replaced with a typedef to the InudstryStandard's.
This doesn't only make it easier to maintain, but it also prevents
potential future issues as the Protocol type has been aligned, while
the standard and the IndustryStandard header declare it as
byte-packed.
This has worked well till now only because the members of the
structure do not require alignment yet.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This is a small convenience function that eases signaling an event group
(identified by GUID). An example where it can be used is Platform BDS
signaling the End-of-DXE event group.
The naming follows EfiNamedEventSignal().
The patch modifies the library class header, and updates the most commonly
used library instance at once. Other library instances in the edk2 tree
will be adapted in the following patches.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Suggested-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The InternalEmptyFunction() is currently only used by code in
"UefiNotTiano.c" -- "Library functions that abstract areas of conflict
between framework and UEFI 2.0.". In the next patches,
InternalEmptyFunction() will be used from "UefiLib.c" as well, hence
promote it to "general utility" status: move the function definition to
"UefiLib.c", and place the function declaration (which is already extern)
into "UefiLibInternal.h".
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add gEfiIa32X64ProcessorErrorSectionGuid and
gEfiArmProcessorErrorSectionGuid to
match the definition in the UEFI 2.6 specification Table 249.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The definition of DEBUG_LOADFILE was incorrectly described as "UNDI
Driver". Correct this to align with MdePkg.dec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Add additional HTTP 1.1 definitions that are useful in HTTP
applications, such as User-Agent, Location, and x-Auth-Token
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Base on the UEFI2.6, Add the new HII action type
EFI_BROWSER_ACTION_SUBMITTED to notify HII driver
when its question values are submitted.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add the definition for the new return status code defined in UEFI 2.6.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The AArch64 DAIF bits are different for reading (mrs) versus writing (msr).
The bitmask definitions assumed they were the same causing incorrect
results when trying to determine the current interrupt state through
GetInterruptState.
The logic for interpreting the DAIF read data using the csel instruction
was also incorrect and is fixed.
Replaced the magic numbers in DisableInterrupts.S and EnableInterrupts.S
with definitions for the DAIF write (daifset/daifclr) IRQ field.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
The HeaderLog field of the PCIe Extended Capabilities Advanced Error
Reporting structure was incorrectly defined as a 32-bit field. The PCIe
2.1 Base Specification, section 7.10, lists this as 16 bytes, or 4
DWORDs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Follow UEFI 2.6 spec to minor update the comments of
AllocatePages() and AllocatePool().
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit also removes common structure definitions between EFI Wireless
MAC Connection Protocol and EFI Wireless MAC Connection II Protocol from
WiFi.h and place them in WiFi2.h.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Recent versions of the Intel C compiler define the _MSC_EXTENSIONS
constant. Base.h checks if this constant is defined to decide whether
or not to use a pragma intrinsic, which is unsupported by the latest
version of the Intel C compiler. Thus the check has been modified to
only pass in the case __INTEL_COMPILER is not defined.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
v2:
*Return the EFI_HTTP_ERROR in the “Status” field in token, instead of
in the status codes returned table of EFI_HTTP_PROTOCOL.Response() interface.
Add a new error status code EFI_HTTP_ERROR in corresponding with
the UEFI 2.6 spec
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>