The value to be written corresponds to hard reset, which is what the ACPI
spec prescribes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14156 6f19259b-4bc3-4df7-8a09-765794883524
This conversion cannot be split very well into smaller patches. Comparing
version 1 and version 2 (modulo the header fields):
> --- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE
> +++ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE
> @@ -1,14 +1,14 @@
> EFI_ACPI_DESCRIPTION_HEADER Header;
> UINT32 FirmwareCtrl;
> UINT32 Dsdt;
> - UINT8 IntModel;
> - UINT8 Reserved1;
> + UINT8 Reserved0;
> + UINT8 PreferredPmProfile;
The INT_MODEL field was present in ACPI 1.0, but eliminated in 2.0.
According to the spec, "platforms should set this field to zero but field
values of one are also allowed to maintain compatibility with ACPI 1.0".
We're setting it to zero.
About Preferred_PM_Profile (taking the place of an 1.0 reserved field),
the specification says:
This field is set by the OEM to convey the preferred power management
profile to OSPM. OSPM can use this field to set default power management
policy parameters during OS installation.
>From <MdePkg/Include/IndustryStandard/Acpi20.h>:
#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0
#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1
#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2
#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3
#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4
#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5
#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6
For a virtual machine, "unspecified" is the best choice.
> UINT16 SciInt;
> UINT32 SmiCmd;
> UINT8 AcpiEnable;
> UINT8 AcpiDisable;
> UINT8 S4BiosReq;
> - UINT8 Reserved2;
> + UINT8 PstateCnt;
We've been already treating this field as PSTATE_CNT. No change in value.
> UINT32 Pm1aEvtBlk;
> UINT32 Pm1bEvtBlk;
> UINT32 Pm1aCntBlk;
> @@ -20,11 +20,11 @@
> UINT8 Pm1EvtLen;
> UINT8 Pm1CntLen;
> UINT8 Pm2CntLen;
> - UINT8 PmTmLen;
> + UINT8 PmTmrLen;
(Field renaming artifact.)
> UINT8 Gpe0BlkLen;
> UINT8 Gpe1BlkLen;
> UINT8 Gpe1Base;
> - UINT8 Reserved3;
> + UINT8 CstCnt;
We've been already treating this field as CST_CNT. No change in value.
> UINT16 PLvl2Lat;
> UINT16 PLvl3Lat;
> UINT16 FlushSize;
> @@ -34,7 +34,19 @@
> UINT8 DayAlrm;
> UINT8 MonAlrm;
> UINT8 Century;
> - UINT8 Reserved4;
> - UINT8 Reserved5;
> - UINT8 Reserved6;
> + UINT16 IaPcBootArch;
> + UINT8 Reserved1;
The first two octets are now merged into a 16-bit short; otherwise we've
been treating those as boot architecture flags already (see SVN rev
13615). No change in value.
> UINT32 Flags;
The fixed feature flags are not modified, only the macro names (expanding
to identical values) are updated to ACPI 2.0.
The following fields are all new in ACPI 2.0:
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;
> + UINT8 ResetValue;
We don't claim support for the reset register yet.
> + UINT8 Reserved2[3];
> + UINT64 XFirmwareCtrl;
> + UINT64 XDsdt;
The 64-bit physical addresses for the FACS and the DSDT are automatically
filled at installation time, see AddTableToList() and DeleteTable() in
"MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableProtocol.c".
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;
> + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;
We specify the extended addresses for the required and supported PM1a
Event & Control, PM Timer, and GPE0 Register Blocks, and zero the rest, in
accordance with the ACPI 1.0 fields.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14155 6f19259b-4bc3-4df7-8a09-765794883524
In the next patch we're going to specify Extended Addresses of register
blocks in Generic Address Structure format. The GAS is easy to fill if we
want to posit either "unsupported" (all zero) or a given address in a
specific address space. However deriving "unsupported" just from a macro
expanding to zero is unwieldy, so let's avoid the need.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14154 6f19259b-4bc3-4df7-8a09-765794883524
Soon we're going to specify Extended Addresses of register blocks in
Generic Address Structure format. The GAS is easy to fill if we want to
posit either "unsupported" (all zero) or a given address in a specific
address space. However deriving "unsupported" just from a macro expanding
to zero is unwieldy, so let's avoid the need.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14153 6f19259b-4bc3-4df7-8a09-765794883524
Soon we're going to specify Extended Addresses of register blocks in
Generic Address Structure format. The GAS is easy to fill if we want to
posit either "unsupported" (all zero) or a given address in a specific
address space. However deriving "unsupported" just from a macro expanding
to zero is unwieldy, so let's avoid the need.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14152 6f19259b-4bc3-4df7-8a09-765794883524
Represent the set of possible PCI link target IRQs with
Pcd8259LegacyModeEdgeLevel. This ensures that the 8259 Interrupt
Controller code in PcAtChipsetPkg will treat them as level-triggered too.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13628 6f19259b-4bc3-4df7-8a09-765794883524
"RTC day of the month alarm feature is not supported".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13614 6f19259b-4bc3-4df7-8a09-765794883524
- Qemu's PIIX emulation actually supports SMM and ACPI_ENABLE /
ACPI_DISABLE.
- After enabling SMI_CMD (SMI_CMD_IO_PORT), further values to be written
there must be synchronized with qemu: PSTATE_CNT, CST_CNT.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13611 6f19259b-4bc3-4df7-8a09-765794883524
0xb000 is the address normally used with QEMU.
0x400 also appears to conflict with some debug I/O ports
used by QEMU.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13279 6f19259b-4bc3-4df7-8a09-765794883524
OVMF does not support SMM. Previously the port value
was set to 0. This should be enough to disable the
SMM ACPI Enable/Disable code paths, but to be
consistent we'll set these fields to 0 as well.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13277 6f19259b-4bc3-4df7-8a09-765794883524
QEMU hard codes the GPE0 registers at 0xafe0.
Previously the code assumed that the GPE0 block
would move when the PM Base Address of the PIIX4
PCI device was programmed. It appears QEMU does not
emulate this behaviour of the PIIX4 PCI device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524
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