2 Commits

Author	SHA1	Message	Date
Tuan Phan	f220dcbba8	UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode ... During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>	2023-07-15 14:10:18 +00:00
Sunil V L	92b27c2e6a	OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform ... REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>	2023-02-16 05:53:28 +00:00