Commit Graph

22 Commits

Author SHA1 Message Date
Evan Lloyd ff1f27c055 ArmPkg: Configure TTBCR register
Architecturally, the TTBCR register value is undefined at reset for
Non-Secure.
On some platforms the reset value for TTBCR is not zero and
this causes a data abort exception once the MMU is enabled.

This patch configures the TTBCR register to enable translation table
walk using TTBR0.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2016-03-03 18:23:54 +00:00
Ard Biesheuvel 46ff196fde ArmPkg/ArmV7Mmu: prefer non shareable memory on non-coherent hardware
Commit SVN r18778 made all mappings of normal memory (inner) shareable,
even on hardware that implements shareability as uncached accesses.
The original concerns that prompted the change, regarding coherent DMA
and virt guests migrating between CPUs, do not apply to such hardware,
so revert to the original behavior in that case.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19285 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 17:31:56 +00:00
Ard Biesheuvel 2cde2696f5 ArmLib/ArmV7Mmu: use 64-bit type for mapping region size
The way the v7 MMU code is invoked by the Xen port is somewhat of
a pathological case, since it describes its physical memory space
using a single cacheable region that covers the entire addressable
range. When clipping this region to the part that is 1:1 addressable,
we end up with a region of exactly 4 GB in size, which just exceeds
the range of the UINT32 variable we use in FillTranslationTable() to
track our progress while populating the page tables. So promote it
to UINT64 instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18930 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-24 07:48:06 +00:00
Ard Biesheuvel 55df704dd2 ArmPkg/ArmV7Mmu: handle memory regions over 4 GB correctly
The ARM_MEMORY_REGION_DESCRIPTOR array provided by the platform may
contain entries that extend beyond the 4 GB boundary, above which
we can't map anything on 32-bit ARM. If this is the case, map only
the 1:1 addressable part.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18900 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 16:18:40 +00:00
Ard Biesheuvel 72143137f4 ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBR
Bits 0 and 6 of the TTBRx system registers have different meanings
depending on whether a system implements the Multiprocessing
Extensions. So use separate memory attribute definitions for MP and
non-MP.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:59 +00:00
Ard Biesheuvel 65ceda9173 ArmPkg/ArmV7Mmu: introduce feature PCD to map normal memory non-shareable
Even though mapping normal memory (inner) shareable is usually the
correct choice on coherent systems, it may be desirable in some cases
to use non-shareable mappings for normal memory, e.g., when hardware
managed coherency is not required and the memory system is not fully
configured yet. So introduce a PCD PcdNormalMemoryNonshareableOverride
that makes cacheable mappings of normal memory non-shareable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18897 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:22 +00:00
Ard Biesheuvel 07070ecc76 ArmPkg/ArmV7Mmu: make cached translation table accesses shareable
To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:59:04 +00:00
Ard Biesheuvel a6ec831c10 ArmPkg/ArmV7Mmu: fix write-through translation table accesses
The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since
a) its meaning is unclear in the context of TTBRx, since write through
   always implies Read-Allocate and no Write-Allocate
b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC

So instead, rename it to TTBR_WRITE_THROUGH and update the definition
to reflect the name.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 15:58:03 +00:00
Ard Biesheuvel 6bc35cbaca ArmPkg/Mmu: set required XN attributes for device mappings
To prevent speculative intruction fetches from MMIO ranges that may
have side effects on reads, the architecture requires device mappings
to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and
EL1&0 translation regimes, respectively.)

Note that, in the ARM case, this involves moving all accesses to a
client domain since permission attributes like XN are ignored from
a manager domain. The use of a client domain is actually mandated
explicitly by the UEFI spec.

Reported-by: Heyi Guo <heyi.guo@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18 11:51:06 +00:00
Ard Biesheuvel 4d9a4f62cf ArmPkg/ArmLib MMU: add functions to set/clear RO and XN bits on regions
Use the refactored UpdateRegionMapping () to traverse the translation
tables, splitting block entries along the way if required, and apply
a mask + or on each to set or clear the PXN/UXN/XN or RO bits.

For now, the 32-bit ARM versions remain unimplemented.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18587 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-08 18:52:16 +00:00
Ronald Cron 3402aac7d9 ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 13:29:52 +00:00
Eugene Cohen ffb91edfd5 ArmPkg/ArmLib: Improved ArmConfigureMmu Performance
Data & Instruction Caches can be kept enabled while the new
translation table is filled.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15647 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-09 11:14:36 +00:00
Olivier Martin 6adbd5b4d2 ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()
This helper function converts the section attributes into their page equivalents.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:37:50 +00:00
Olivier Martin a3202839da ArmPkg/ArmLib: Marked functions as 'STATIC' if not exposed outside of the scope of the source file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14446 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27 18:17:19 +00:00
Olivier Martin 6f050ad6bf ArmPkg: Made ArmConfigureMmu() returns a status code
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14445 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27 18:16:06 +00:00
Olivier Martin 918c653e1f ArmPkg/ArmLib: Removed ArmInvalidateTlb when disabling cache as ArmDisableMmu() already does it
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14436 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19 18:27:55 +00:00
oliviermartin 526099f968 ArmPkg/ArmLib: Fixed parameter checking in ArmConfigureMmu()
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13429 6f19259b-4bc3-4df7-8a09-765794883524
2012-06-06 15:47:23 +00:00
oliviermartin 7fffeef9be ARM Packages: Fixed th 'NS' (Non Secure) bit in the MMU page Table Descriptor
The 'NS' bit must only be set in Secure world to define the Non-Secure region
of the Non-Secure World.
This bit must not be set in Non-Secure World.

Signed-off-by: Olivier Martin <olivier.martin@arm.com>


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13252 6f19259b-4bc3-4df7-8a09-765794883524
2012-05-02 20:00:54 +00:00
oliviermartin 5ed2368498 ArmPkg/ArmLib: Fixed 'ArmConfigureMmu()' to avoid overflow when an entry is mapped at 0xFFFFFFFF
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13056 6f19259b-4bc3-4df7-8a09-765794883524
2012-02-28 17:20:34 +00:00
oliviermartin bd6b97994a ArmPkg/ArmLib: Clean ArmV7Lib
- Move the non specific ArmV7 functions to ArmLib.
- Clean the ARM Platform common components to not depend on ArmV7 if not required



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27 16:31:20 +00:00
oliviermartin 2cf4b60895 ArmPkg/Mmu: Support page size granularity in the initial MMU setting
Formerly, it was only possible to use section size granularity for the
translation table regions.
This change allows to define initial translation table regions with
4K-byte granularty (page size granularity).



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11467 6f19259b-4bc3-4df7-8a09-765794883524
2011-03-31 11:23:55 +00:00
andrewfish 1bfda055df Sync up ArmPkg with patch from mailing list. Changed name of BdsLib.h to BdsUnixLib.h and fixed a lot of issues with Xcode building.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
2011-02-02 22:35:30 +00:00