This is a new PPI introduced in PI 1.4 to pass multiple CPU information from
SEC phase to PEI/DXE phases.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17640 6f19259b-4bc3-4df7-8a09-765794883524
Jeff Fan