UEFI 2.5 Spec:
MemoryType values in the range 0x70000000..0x7FFFFFFF
are reserved for OEM use.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17459 6f19259b-4bc3-4df7-8a09-765794883524
Multi-processor PPI header file 'Ppi/Mpservices.h' uses a function
prototype EFI_AP_PROCEDURE which is defined in 'Pi/PiDxeCis.h' (DXE header
file).
This will cause a build fail when 'Ppi/Mpservices.h' is included in a PEI
module.
Since both phase support multi-processor service now, function prototype
EFI_AP_PROCEDURE should be moved to 'Pi/PiMultiPhase.h'. The move is a
compatible change and will not affect other codes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17450 6f19259b-4bc3-4df7-8a09-765794883524
The old implementation was to allocate EfiBootServicesData memory first,
and then update the MemoryType of memory allocation hob to
EfiReservedMemoryType.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17395 6f19259b-4bc3-4df7-8a09-765794883524
Declares some extern EFI_GUID variables which correspond to
guid macros in SmartCardEdge.h for C code use.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17379 6f19259b-4bc3-4df7-8a09-765794883524
Declares some extern EFI_GUID variables which correspond to
guid macros in BlockIoCrypto.h for C code use.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17378 6f19259b-4bc3-4df7-8a09-765794883524
It's to follow the PI spec 1.4.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jie Lin <jie.lin@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17367 6f19259b-4bc3-4df7-8a09-765794883524
Use pragma to disable warning 4200 for all VS* and DDK* tool chains to support
data structure declarations where the last field of the data structure is a
flexible array member.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: lhauch <larry.hauch@intel.com>
Tested-by: Chao Zhang <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17361 6f19259b-4bc3-4df7-8a09-765794883524
To support GPI number > 64, PI 1.4 clarified SMM GpiNum meaning as below:
typedef struct {
UINT64 GpiNum;
} EFI_SMM_GPI_REGISTER_CONTEXT;
Instead of the bit mask of 64 possible GPIs, GpiNum is one of 2^64 possible
GPIs that can generate an SMI. A 0 corresponds to logical GPI[00],
1 corresponds to logical GPI[1], and so on, and GpiNum of N corresponds to
GPI[N], where N can span from 0 to 2^64-1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17350 6f19259b-4bc3-4df7-8a09-765794883524
PI 1.4 clarified SMM register protocol notify function return status as below:
EFI_SUCCESS Successfully returned the registration record that has
been added or unhooked
EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17348 6f19259b-4bc3-4df7-8a09-765794883524
The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly
implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register.
The EBX register value is saved onto the stack before CPUID and restored from the stack
after CPUID.
The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the
LinearAddress parameter value on the stack. The hardcoded lookup using [esp + 4] is not correct.
Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent
this issue from occurring again if there are changes to the inline assembly in the future.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524
Add new information block ‘IPV6 support from UNDI’ in AIP protocol and provide sample implementation in UNDI driver.
Update PXE driver to get ‘Ipv6Available’ of PXE BC Mode data from UNDI driver, if unsupported then not to start PXE over IPv6 path.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17275 6f19259b-4bc3-4df7-8a09-765794883524
These definitions are defined in UEFI2.5/PI1.4 spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17245 6f19259b-4bc3-4df7-8a09-765794883524
Star Zeng
Hao Wu
Feng Tian
Eric Dong
Chao Zhang
Ruiyu Ni
Liming Gao
Michael Kinney
Jeff Fan
Qiu Shumin
Yao, Jiewen
Ye Ting