Commit Graph

4 Commits

Author SHA1 Message Date
Star Zeng bac7f02365 IntelSiliconPkg IntelVTdDxe: Fix flush cache issue
The patch fixes flush cache issue in
CreateSecondLevelPagingEntryTable().

We found some video cards still not work even they have
been added to the exception list.

In CreateSecondLevelPagingEntryTable(), the check
"(BaseAddress >= MemoryLimit)" may be TRUE and "goto Done"
will be executed, then the FlushPageTableMemory operations
at the end of the function will be skipped.

Instead of "goto Done", this patch uses "break" to break
the for loops, then the FlushPageTableMemory operations
at the end of the function could have opportunity to be
executed.

The patch also fixes a miscalculation for Lvl3End.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-24 18:40:36 +08:00
Star Zeng 1d4c17a6ef IntelSiliconPkg IntelVTdDxe: Fix DMA does not work issue
Fix DMA does not work issue when system memory is not
greater than 4G.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2018-01-18 10:36:56 +08:00
Jiewen Yao 73a2fe8b87 IntelSiliconPkg/VTdDxe: Clean up DXE flush memory.
Make sure the context table are flush to memory.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-23 16:14:27 +08:00
Jiewen Yao 9010459c9a IntelSiliconPkg/IntelVTdDxe: Move to feature dir.
Move IntelVTdDxe to Feature/VTd/IntelVTdDxe.

Suggested-by: Star Zeng <star.zeng@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-17 09:52:10 +08:00