The Index Register Base Address bitfield is selected by the binary mask
00000000 00000000 11111111 11000000, 0xFFC0; fix the typo.
Reported-by: Gleb Natapov <gleb@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13720 6f19259b-4bc3-4df7-8a09-765794883524
0xb000 is the address normally used with QEMU.
0x400 also appears to conflict with some debug I/O ports
used by QEMU.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13279 6f19259b-4bc3-4df7-8a09-765794883524
For the first instance of the library that runs, the
base is initialized to 0x400, but we access it at 0x401.
Signed-off-by: jljusten
Reviewed-by: niruiyu
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12121 6f19259b-4bc3-4df7-8a09-765794883524
If PIIX4 Power Management Base Address (PMBA) is already
programmed, then read and use it's current setting.
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
Reviewed-by: gavinguan
Signed-off-by: jljusten
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12053 6f19259b-4bc3-4df7-8a09-765794883524
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