1. Update fdf and dsc to use SerialDxe in MdeModulePkg.
2. Separate the code that gets SerialRegBase and SerialRegAccessType
by CbParseLib from CorebootPayloadPkg/Library/SerialPortLib to
PlatformHookLib, and then leverage BaseSerialPortLib16550 in
MdeModulePkg.
3. Remove CorebootPayloadPkg/SerialDxe and
CorebootPayloadPkg/Library/SerialPortLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18968 6f19259b-4bc3-4df7-8a09-765794883524
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc doesn't use any X64
modules, so it should not specify the X64 architecture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18073 6f19259b-4bc3-4df7-8a09-765794883524
Current CorebootPayloadPkg uses PciHostBridge and PciBusNoEnumeration
driver. It will cause the PCI bus resource incorrectly set in root
bridge instance. As a result all PCI devices behind a PCI bridge will
not show up in Shell 'PCI' command.
To resolve it use PciRootBridgeNoEnumeration driver instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17408 6f19259b-4bc3-4df7-8a09-765794883524
Use the example.com domain as recommended in RFC 2606.
This was changed for the other EDK II packages in r16724.
NOTE: This does not modify the wording of the "TianoCore Contribution
Agreement 1.0" section
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17169 6f19259b-4bc3-4df7-8a09-765794883524
In current CorebootPayloadPkg.dec an empty 'Include' directory is
listed in [includes] section. However, this empty directory will
not be mirrored into git repo. If the source tree is pulled from git,
the 'Include' empty folder will not exist and it will cause build
failure. The fix is to remove the whole [Includes] section in the
DEC file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17164 6f19259b-4bc3-4df7-8a09-765794883524
Enable use of 1GB pages to avoid page table memory allocation failure.
The failure occurs when allocating enough 4KB pages to map a large
virtual address space, such as the 48-bit virtual address space of AMD
family 10h and family 15h processors. The change is needed only for the
X64 build because page tables are not used by the IA32 build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17151 6f19259b-4bc3-4df7-8a09-765794883524
Use unique output directory names so that both IA32 and X64 payloads
can be built without overwriting one another.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17150 6f19259b-4bc3-4df7-8a09-765794883524
Add NOOPT build to accommodate source level debugging. The NOOPT build
avoids the use of compiler optimization so that every local variable is
accessible by a source level debugger.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17149 6f19259b-4bc3-4df7-8a09-765794883524
Increase payload size limit to accomodate large binaries, such as those
produced by Microsoft NOOPT builds and gcc DEBUG builds.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17148 6f19259b-4bc3-4df7-8a09-765794883524
Use extra braces around initialization data to prevent gcc compile
error: -Werror=missing-braces.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17147 6f19259b-4bc3-4df7-8a09-765794883524
Initial coreboot UEFI payload code check in. It provides UEFI services on top of coreboot that allows UEFI OS boot.
CorebootPayloadPkg is source code package of coreboot Payload Modules, Provides definitions of payload image's layout and lists the modules required in DSC file.
It supports the following features:
- Support Unified Extensible Firmware Interface (UEFI) specification 2.4.
- Support Platform Initialization(PI) specification 1.3.
- Support execution as a coreboot payload.
- Support USB 3.0
- Support SATA/ATA devices.
- Support EFI aware OS boot.
The following features are not supported currently and have not been validated:
- GCC Tool Chains
- SMM Execution Environment
- Security Boot
It was tested on a Intel Bay Trail CRB platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17081 6f19259b-4bc3-4df7-8a09-765794883524
Leahy, Leroy P
Star Zeng
Jordan Justen
Guo Dong
Maurice Ma
Ruiyu Ni
Scott Duplichan
laurie0131