## @file # IntelSilicon Package # # This package provides common open source Intel silicon modules. # # Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## [Defines] DEC_SPECIFICATION = 0x00010005 PACKAGE_NAME = IntelSiliconPkg PACKAGE_GUID = F7A58914-FA0E-4F71-BD6A-220FDF824A49 PACKAGE_VERSION = 0.1 [Includes] Include [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides services to access Microcode region on flash device. # MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h [Guids] ## GUID for Package token space # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735} gIntelSiliconPkgTokenSpaceGuid = { 0xa9f8d54e, 0x1107, 0x4f0a, { 0xad, 0xd0, 0x45, 0x87, 0xe7, 0xa4, 0xa7, 0x35 } } ## HOB GUID to publish SMBIOS data records from PEI phase # HOB data format is same as SMBIOS records defined in SMBIOS spec or OEM defined types # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records into SMBIOS table gIntelSmbiosDataHobGuid = { 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }} ## Include/Guid/MicrocodeFmp.h gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } [Ppis] gEdkiiVTdInfoPpiGuid = { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } [Protocols] gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR = (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x02008000
# @Prompt Error code for VTd error. gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT) # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver. # The default GUID can be updated by patching or runtime if platform support multiple VBT configurations. # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (VBT) # { 0x56752da9, 0xde6b, 0x4895, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 } gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d, 0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c, 0x22 }|VOID*|0x00000001 ## The mask is used to control VTd behavior.

# BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.) # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in normal boot. EndOfPEI in S3) # BIT2: Force no IOMMU access attribute request recording before DMAR table is installed. # @Prompt The policy for VTd driver behavior. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002 ## Declares VTd PEI DMA buffer size.

# When this PCD value is referred by platform to calculate the required # memory size for PEI (InstallPeiMemory), the PMR alignment requirement # needs be considered to be added with this PCD value for alignment # adjustment need by AllocateAlignedPages. # @Prompt The VTd PEI DMA buffer size. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|0x00000003 ## Declares VTd PEI DMA buffer size for S3.

# When this PCD value is referred by platform to calculate the required # memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirement # needs be considered to be added with this PCD value for alignment # adjustment need by AllocateAlignedPages. # @Prompt The VTd PEI DMA buffer size for S3. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT32|0x00000004