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A potential issue may happen when FSP creates/changes page table while bootloader doesn't expect page table being changed in FSP. Current, FSP API support to save/restore stack, IDT and general purpose registers. Following the same pattern, add save/restore page table support to solve this issue. Note that this feature only impacts FSP API mode, and is controlled by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD default value is set as FALSE. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
304 lines
8.1 KiB
NASM
304 lines
8.1 KiB
NASM
;; @file
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; Provide FSP API entry points.
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;
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; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;;
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SECTION .text
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;
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; Following are fixed PCDs
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;
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extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
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extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
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extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
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extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
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struc FSPM_UPD_COMMON
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; FSP_UPD_HEADER {
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.FspUpdHeader: resd 8
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; }
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; FSPM_ARCH_UPD {
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.Revision: resb 1
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.Reserved: resb 3
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.NvsBufferPtr: resd 1
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.StackBase: resd 1
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.StackSize: resd 1
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.BootLoaderTolumSize: resd 1
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.BootMode: resd 1
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.Reserved1: resb 8
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; }
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.size:
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endstruc
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struc FSPM_UPD_COMMON_FSP24
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; FSP_UPD_HEADER {
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.FspUpdHeader: resd 8
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; }
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; FSPM_ARCH2_UPD {
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.Revision: resb 1
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.Reserved: resb 3
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.Length resd 1
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.NvsBufferPtr resq 1
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.StackBase: resq 1
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.StackSize: resq 1
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.BootLoaderTolumSize: resd 1
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.BootMode: resd 1
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.FspEventHandler resq 1
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.Reserved1: resb 16
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; }
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.size:
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endstruc
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;
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; Following functions will be provided in C
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;
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extern ASM_PFX(SecStartup)
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extern ASM_PFX(FspApiCommon)
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;
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; Following functions will be provided in PlatformSecLib
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;
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extern ASM_PFX(AsmGetFspBaseAddress)
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extern ASM_PFX(AsmGetFspInfoHeader)
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API_PARAM1_OFFSET EQU 44h ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER +pushad + pushfd + push eax + call]
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FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
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FSP_HEADER_CFGREG_OFFSET EQU 24h
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;----------------------------------------------------------------------------
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; FspMemoryInit API
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;
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; This FSP API is called after TempRamInit and initializes the memory.
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspMemoryInitApi)
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ASM_PFX(FspMemoryInitApi):
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mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; TempRamExitApi API
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;
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; This API tears down temporary RAM
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(TempRamExitApi)
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ASM_PFX(TempRamExitApi):
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mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex
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jmp ASM_PFX(FspApiCommon)
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;----------------------------------------------------------------------------
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; FspApiCommonContinue API
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;
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; This is the FSP API common entry point to resume the FSP execution
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(FspApiCommonContinue)
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ASM_PFX(FspApiCommonContinue):
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;
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; EAX holds the API index
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;
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;
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; FspMemoryInit API setup the initial stack frame
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;
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;
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; Place holder to store the FspInfoHeader pointer
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;
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push eax
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;
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; Update the FspInfoHeader pointer
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;
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push eax
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call ASM_PFX(AsmGetFspInfoHeader)
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mov [esp + 4], eax
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pop eax
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;
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; Create a Task Frame in the stack for the Boot Loader
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;
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pushfd ; 2 pushf for 4 byte alignment
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cli
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pushad
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;
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; Allocate 4x4 bytes on the stack.
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;
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sub esp, 16
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cmp byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
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jz SkipPagetableSave
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add esp, 16
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; Save EFER MSR lower 32-bit
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push ecx
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push eax
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mov ecx, 0xC0000080
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rdmsr
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mov edx, eax
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pop eax
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pop ecx
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push edx
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; Save CR registers
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mov edx, cr4
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push edx
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mov edx, cr3
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push edx
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mov edx, cr0
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push edx
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SkipPagetableSave:
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; Reserve 8 bytes for IDT save/restore
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sub esp, 8
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sidt [esp]
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; Get Stackbase and StackSize from FSPM_UPD Param
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mov edx, [esp + API_PARAM1_OFFSET]
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cmp edx, 0
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jnz FspStackSetup
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; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null
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push eax
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call ASM_PFX(AsmGetFspInfoHeader)
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mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET]
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add edx, [eax + FSP_HEADER_CFGREG_OFFSET]
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pop eax
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FspStackSetup:
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mov ecx, [edx + FSPM_UPD_COMMON.Revision]
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cmp ecx, 3
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jae FspmUpdCommon2
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;
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; StackBase = temp memory base, StackSize = temp memory size
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;
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mov edi, [edx + FSPM_UPD_COMMON.StackBase]
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mov ecx, [edx + FSPM_UPD_COMMON.StackSize]
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jmp ChkFspHeapSize
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FspmUpdCommon2:
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mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
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mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
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ChkFspHeapSize:
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;
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; Keep using bootloader stack if heap size % is 0
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;
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mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))]
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cmp bl, 0
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jz SkipStackSwitch
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;
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; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't equal 0
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;
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add edi, ecx
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;
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; Switch to new FSP stack
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;
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xchg edi, esp ; Exchange edi and esp, edi will be assigned to the current esp pointer and esp will be Stack base + Stack size
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SkipStackSwitch:
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;
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; If heap size % is 0:
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; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loader stack pointer)
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; ECX is FSPM_UPD_COMMON.StackSize
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; ESP is boot loader stack pointer (no stack switch)
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; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.StackBase later)
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;
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; If heap size % is not 0
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; EDI is boot loader stack pointer
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; ECX is FSPM_UPD_COMMON.StackSize
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; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackSize)
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; BL is NOT 0 to indicate stack has switched
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;
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cmp bl, 0
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jnz StackHasBeenSwitched
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mov ebx, edi ; Put FSPM_UPD_COMMON.StackBase to ebx as temp memory base
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mov edi, esp ; Put boot loader stack pointer to edi
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jmp StackSetupDone
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StackHasBeenSwitched:
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mov ebx, esp ; Put Stack base + Stack size in ebx
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sub ebx, ecx ; Stack base + Stack size - Stack size as temp memory base
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StackSetupDone:
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;
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; Pass the API Idx to SecStartup
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;
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push eax
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;
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; Pass the BootLoader stack to SecStartup
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;
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push edi
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;
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; Pass entry point of the PEI core
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;
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call ASM_PFX(AsmGetFspBaseAddress)
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mov edi, eax
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call ASM_PFX(AsmGetPeiCoreOffset)
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add edi, eax
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push edi
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;
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; Pass BFV into the PEI Core
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; It uses relative address to calculate the actual boot FV base
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; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
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; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
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; they are different. The code below can handle both cases.
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;
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call ASM_PFX(AsmGetFspBaseAddress)
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push eax
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;
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; Pass stack base and size into the PEI Core
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;
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push ebx
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push ecx
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;
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; Pass Control into the PEI Core
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;
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call ASM_PFX(SecStartup)
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add esp, 4
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exit:
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ret
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global ASM_PFX(FspPeiCoreEntryOff)
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ASM_PFX(FspPeiCoreEntryOff):
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;
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; This value will be patched by the build script
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;
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DD 0x12345678
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global ASM_PFX(AsmGetPeiCoreOffset)
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ASM_PFX(AsmGetPeiCoreOffset):
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mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)]
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ret
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;----------------------------------------------------------------------------
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; TempRamInit API
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;
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; Empty function for WHOLEARCHIVE build option
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;
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;----------------------------------------------------------------------------
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global ASM_PFX(TempRamInitApi)
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ASM_PFX(TempRamInitApi):
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jmp $
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ret
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;----------------------------------------------------------------------------
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; Module Entrypoint API
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;----------------------------------------------------------------------------
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global ASM_PFX(_ModuleEntryPoint)
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ASM_PFX(_ModuleEntryPoint):
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jmp $
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