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550f196e82
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
32 lines
790 B
ArmAsm
32 lines
790 B
ArmAsm
//------------------------------------------------------------------------------
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//
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// CPU scratch register related functions for RISC-V
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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#include <Register/RiscV64/RiscVImpl.h>
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.data
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.align 3
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.section .text
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//
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// Set Supervisor mode scratch.
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// @param a0 : Value set to Supervisor mode scratch
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//
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ASM_FUNC (RiscVSetSupervisorScratch)
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csrw CSR_SSCRATCH, a0
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ret
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//
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// Get Supervisor mode scratch.
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// @retval a0 : Value in Supervisor mode scratch
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//
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ASM_FUNC (RiscVGetSupervisorScratch)
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csrr a0, CSR_SSCRATCH
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ret
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