mirror of
https://github.com/acidanthera/audk.git
synced 2025-08-24 02:58:10 +02:00
8ae17a71af
stimecmp is a CSR supported only when Sstc extension is supported by the platform. This register can be used to set the timer interrupt directly in S-mode instead of going via SBI call. Add a function to update this register. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
31 lines
675 B
ArmAsm
31 lines
675 B
ArmAsm
//------------------------------------------------------------------------------
|
|
//
|
|
// Read CPU timer
|
|
//
|
|
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
|
//
|
|
// SPDX-License-Identifier: BSD-2-Clause-Patent
|
|
//
|
|
//------------------------------------------------------------------------------
|
|
|
|
#include <Register/RiscV64/RiscVImpl.h>
|
|
|
|
.data
|
|
.align 3
|
|
.section .text
|
|
|
|
//
|
|
// Read TIME CSR.
|
|
// @retval a0 : 64-bit timer.
|
|
//
|
|
ASM_FUNC (RiscVReadTimer)
|
|
csrr a0, CSR_TIME
|
|
ret
|
|
|
|
//
|
|
// Set Supervisor Time Compare Register
|
|
//
|
|
ASM_FUNC (RiscVSetSupervisorTimeCompareRegister)
|
|
csrw CSR_STIMECMP, a0
|
|
ret
|