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c1eb477e06
Refer to intel-tdx-module-api spec section 5.5.21, GPR mask (TDVMCALL_EXPOSE_REGS_MASK) is a bitmap that controls which part of the guest TD GPR and XMM state is passed as-is to the VMM and back. - A bit value of 0 indicates that the corresponding register is saved by the Intel TDX module and not passed as-is to Host VMM. - A bit value of 1 indicates that the corresponding register is passed as-is to the host VMM. Currently, RBX is used as the mailbox address in ApRunLoop.nasm, the corresponding bit value of RBX in MASK(Bit 3) is set as 1 which means the value is passed to Host VMM as-is and it can be changed by Host VMM. So the bitmask shall be set as 0 to avoid this situation. Reference: [TDX-API]: intel-tdx-module-abi-spec https://cdrdv2.intel.com/v1/dl/getContent/733579 Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Hunter Adrian <adrian.hunter@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
114 lines
3.1 KiB
NASM
114 lines
3.1 KiB
NASM
;------------------------------------------------------------------------------ ;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; ApRunLoop.nasm
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;
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; Abstract:
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;
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; This is the assembly code for run loop for APs in the guest TD
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;
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;-------------------------------------------------------------------------------
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%include "TdxCommondefs.inc"
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DEFAULT REL
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SECTION .text
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BITS 64
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%define TDVMCALL_EXPOSE_REGS_MASK 0xffc4
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%define TDVMCALL 0x0
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%define EXIT_REASON_CPUID 0xa
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%macro tdcall 0
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db 0x66, 0x0f, 0x01, 0xcc
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%endmacro
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%macro tdcall_regs_preamble 2
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mov rax, %1
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xor rcx, rcx
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mov ecx, %2
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; R10 = 0 (standard TDVMCALL)
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xor r10d, r10d
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; Zero out unused (for standard TDVMCALL) registers to avoid leaking
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; secrets to the VMM.
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xor esi, esi
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xor edi, edi
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xor edx, edx
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xor ebp, ebp
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xor r8d, r8d
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xor r9d, r9d
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xor r14, r14
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xor r15, r15
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%endmacro
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;
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; Relocated Ap Mailbox loop
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;
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; @param[in] RBX: Relocated mailbox address
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; @param[in] RBP: vCpuId
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;
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; @return None This routine does not return
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;
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global ASM_PFX(AsmRelocateApMailBoxLoop)
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ASM_PFX(AsmRelocateApMailBoxLoop):
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AsmRelocateApMailBoxLoopStart:
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mov r11, EXIT_REASON_CPUID
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mov r12, 0xb
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tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK
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tdcall
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test r10, r10
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jnz Panic
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mov r8, r15
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MailBoxLoop:
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; Spin until command set
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cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandNoop
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je MailBoxLoop
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; Determine if this is a broadcast or directly for my apic-id, if not, ignore
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cmp dword [rbx + ApicidOffset], MailboxApicidBroadcast
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je MailBoxProcessCommand
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cmp dword [rbx + ApicidOffset], r8d
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jne MailBoxLoop
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MailBoxProcessCommand:
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cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandWakeup
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je MailBoxWakeUp
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cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandSleep
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je MailBoxSleep
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; Don't support this command, so ignore
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jmp MailBoxLoop
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MailBoxWakeUp:
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mov rax, [rbx + WakeupVectorOffset]
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; OS sends a wakeup command for a given APIC ID, firmware is supposed to reset
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; the command field back to zero as acknowledgement.
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mov qword [rbx + CommandOffset], 0
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jmp rax
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MailBoxSleep:
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jmp $
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Panic:
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ud2
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BITS 64
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AsmRelocateApMailBoxLoopEnd:
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;-------------------------------------------------------------------------------------
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; AsmGetRelocationMap (&RelocationMap);
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;-------------------------------------------------------------------------------------
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global ASM_PFX(AsmGetRelocationMap)
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ASM_PFX(AsmGetRelocationMap):
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lea rax, [AsmRelocateApMailBoxLoopStart]
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mov qword [rcx], rax
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mov qword [rcx + 8h], AsmRelocateApMailBoxLoopEnd - AsmRelocateApMailBoxLoopStart
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ret
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