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550f196e82
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
109 lines
2.8 KiB
ArmAsm
109 lines
2.8 KiB
ArmAsm
//------------------------------------------------------------------------------
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//
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// RISC-V Supervisor Mode interrupt enable/disable
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//
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// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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//
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// SPDX-License-Identifier: BSD-2-Clause-Patent
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//
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//------------------------------------------------------------------------------
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#include <Register/RiscV64/RiscVImpl.h>
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ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
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ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
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ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
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#define SSTATUS_SPP_BIT_POSITION 8
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//
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// This routine disables supervisor mode interrupt
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//
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ASM_PFX(RiscVDisableSupervisorModeInterrupts):
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add sp, sp, -(__SIZEOF_POINTER__)
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sd a1, (sp)
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li a1, SSTATUS_SIE
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csrc CSR_SSTATUS, a1
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ld a1, (sp)
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add sp, sp, (__SIZEOF_POINTER__)
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ret
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//
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// This routine enables supervisor mode interrupt
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//
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ASM_PFX(RiscVEnableSupervisorModeInterrupt):
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add sp, sp, -2*(__SIZEOF_POINTER__)
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sd a0, (0*__SIZEOF_POINTER__)(sp)
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sd a1, (1*__SIZEOF_POINTER__)(sp)
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csrr a0, CSR_SSTATUS
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and a0, a0, (1 << SSTATUS_SPP_BIT_POSITION)
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bnez a0, InTrap // We are in supervisor mode (SMode)
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// trap handler.
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// Skip enabling SIE becasue SIE
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// is set to disabled by RISC-V hart
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// when the trap takes hart to SMode.
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li a1, SSTATUS_SIE
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csrs CSR_SSTATUS, a1
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InTrap:
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ld a0, (0*__SIZEOF_POINTER__)(sp)
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ld a1, (1*__SIZEOF_POINTER__)(sp)
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add sp, sp, 2*(__SIZEOF_POINTER__)
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ret
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//
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// Set Supervisor mode trap vector.
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// @param a0 : Value set to Supervisor mode trap vector
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//
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ASM_FUNC (RiscVSetSupervisorStvec)
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csrrw a1, CSR_STVEC, a0
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ret
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//
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// Get Supervisor mode trap vector.
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// @retval a0 : Value in Supervisor mode trap vector
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//
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ASM_FUNC (RiscVGetSupervisorStvec)
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csrr a0, CSR_STVEC
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ret
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//
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// Get Supervisor trap cause CSR.
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//
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ASM_FUNC (RiscVGetSupervisorTrapCause)
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csrrs a0, CSR_SCAUSE, 0
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ret
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//
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// This routine returns supervisor mode interrupt
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// status.
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//
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ASM_FUNC (RiscVGetSupervisorModeInterrupts)
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csrr a0, CSR_SSTATUS
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andi a0, a0, SSTATUS_SIE
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ret
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//
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// This routine disables supervisor mode timer interrupt
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//
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ASM_FUNC (RiscVDisableTimerInterrupt)
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li a0, SIP_STIP
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csrc CSR_SIE, a0
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ret
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//
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// This routine enables supervisor mode timer interrupt
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//
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ASM_FUNC (RiscVEnableTimerInterrupt)
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li a0, SIP_STIP
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csrs CSR_SIE, a0
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ret
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//
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// This routine clears pending supervisor mode timer interrupt
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//
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ASM_FUNC (RiscVClearPendingTimerInterrupt)
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li a0, SIP_STIP
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csrc CSR_SIP, a0
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ret
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