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Cache maintenance operations by set/way are not broadcast, and operate on individual architected caches, making them suitable only for en/disabling cache levels, which is the job of secure firmware, to be carried out while the CPU in question is not taking part in the cache coherency protocol. Managing the clean/dirty state of a memory range can only be done using cache maintenance by virtual address. So drop the set/way handling from ArmLib for ARM and AARCH64, as there is no context where it can be used correctly from EDK2. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
98 lines
1.9 KiB
C
98 lines
1.9 KiB
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2021, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/DebugLib.h>
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#include <AArch64/AArch64.h>
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#include "AArch64Lib.h"
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#include "ArmLibPrivate.h"
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/**
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Check whether the CPU supports the GIC system register interface (any version)
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@return Whether GIC System Register Interface is supported
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**/
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BOOLEAN
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EFIAPI
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ArmHasGicSystemRegisters (
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VOID
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)
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{
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return ((ArmReadIdAA64Pfr0 () & AARCH64_PFR0_GIC) != 0);
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}
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/** Checks if CCIDX is implemented.
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@retval TRUE CCIDX is implemented.
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@retval FALSE CCIDX is not implemented.
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**/
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BOOLEAN
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EFIAPI
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ArmHasCcidx (
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VOID
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)
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{
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UINTN Mmfr2;
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Mmfr2 = ArmReadIdAA64Mmfr2 ();
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return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
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}
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/**
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Checks whether the CPU implements the Virtualization Host Extensions.
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@retval TRUE FEAT_VHE is implemented.
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@retval FALSE FEAT_VHE is not mplemented.
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**/
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BOOLEAN
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EFIAPI
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ArmHasVhe (
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VOID
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)
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{
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return ((ArmReadIdAA64Mmfr1 () & AARCH64_MMFR1_VH) != 0);
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}
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/**
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Checks whether the CPU implements the Trace Buffer Extension.
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@retval TRUE FEAT_TRBE is implemented.
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@retval FALSE FEAT_TRBE is not mplemented.
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**/
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BOOLEAN
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EFIAPI
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ArmHasTrbe (
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VOID
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)
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{
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return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRBE) != 0);
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}
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/**
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Checks whether the CPU implements the Embedded Trace Extension.
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@retval TRUE FEAT_ETE is implemented.
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@retval FALSE FEAT_ETE is not mplemented.
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**/
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BOOLEAN
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EFIAPI
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ArmHasEte (
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VOID
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)
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{
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// The ID_AA64DFR0_EL1.TraceVer field identifies the presence of FEAT_ETE.
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return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRACEVER) != 0);
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}
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