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6706fe6e23
Cache maintenance operations by set/way are not broadcast, and operate on individual architected caches, making them suitable only for en/disabling cache levels, which is the job of secure firmware, to be carried out while the CPU in question is not taking part in the cache coherency protocol. Managing the clean/dirty state of a memory range can only be done using cache maintenance by virtual address. So drop the set/way handling from ArmLib for ARM and AARCH64, as there is no context where it can be used correctly from EDK2. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
79 lines
980 B
C
79 lines
980 B
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef AARCH64_LIB_H_
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#define AARCH64_LIB_H_
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UINTN
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EFIAPI
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ArmReadIdAA64Dfr0 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Dfr1 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Isar0 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Isar1 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Isar2 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Mmfr0 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Mmfr1 (
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VOID
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);
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/** Reads the ID_AA64MMFR2_EL1 register.
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@return The contents of the ID_AA64MMFR2_EL1 register.
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**/
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UINTN
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EFIAPI
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ArmReadIdAA64Mmfr2 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Pfr0 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdAA64Pfr1 (
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VOID
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);
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#endif // AARCH64_LIB_H_
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