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6706fe6e23
Cache maintenance operations by set/way are not broadcast, and operate on individual architected caches, making them suitable only for en/disabling cache levels, which is the job of secure firmware, to be carried out while the CPU in question is not taking part in the cache coherency protocol. Managing the clean/dirty state of a memory range can only be done using cache maintenance by virtual address. So drop the set/way handling from ArmLib for ARM and AARCH64, as there is no context where it can be used correctly from EDK2. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
43 lines
828 B
C
43 lines
828 B
C
/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef ARM_V7_LIB_H_
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#define ARM_V7_LIB_H_
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#define ID_MMFR0_SHARELVL_SHIFT 12
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#define ID_MMFR0_SHARELVL_MASK 0xf
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#define ID_MMFR0_SHARELVL_ONE 0
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#define ID_MMFR0_SHARELVL_TWO 1
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#define ID_MMFR0_INNERSHR_SHIFT 28
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#define ID_MMFR0_INNERSHR_MASK 0xf
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#define ID_MMFR0_OUTERSHR_SHIFT 8
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#define ID_MMFR0_OUTERSHR_MASK 0xf
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#define ID_MMFR0_SHR_IMP_UNCACHED 0
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#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
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#define ID_MMFR0_SHR_IGNORED 0xf
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/** Reads the ID_MMFR4 register.
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@return The contents of the ID_MMFR4 register.
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**/
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UINT32
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EFIAPI
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ArmReadIdMmfr4 (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdPfr1 (
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VOID
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);
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#endif // ARM_V7_LIB_H_
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