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6706fe6e23
Cache maintenance operations by set/way are not broadcast, and operate on individual architected caches, making them suitable only for en/disabling cache levels, which is the job of secure firmware, to be carried out while the CPU in question is not taking part in the cache coherency protocol. Managing the clean/dirty state of a memory range can only be done using cache maintenance by virtual address. So drop the set/way handling from ArmLib for ARM and AARCH64, as there is no context where it can be used correctly from EDK2. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
237 lines
6.6 KiB
ArmAsm
237 lines
6.6 KiB
ArmAsm
#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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# Copyright (c) 2016, Linaro Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroLib.h>
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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.set CTRL_M_BIT, (1 << 0)
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.set CTRL_C_BIT, (1 << 2)
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.set CTRL_B_BIT, (1 << 7)
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.set CTRL_I_BIT, (1 << 12)
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.set CTRL_AFE_BIT,(1 << 29)
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ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
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bx lr
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ASM_FUNC(ArmCleanDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
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bx lr
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ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
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mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
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bx lr
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ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
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mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
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mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
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bx lr
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ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
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mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
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bx lr
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ASM_FUNC(ArmInvalidateInstructionCache)
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mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableMmu)
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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orr R0,R0,#CTRL_AFE_BIT
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mcr p15,0,R0,c1,c0,0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableMmu)
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 @Disable MMU
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mcr p15,0,R0,c8,c7,0 @Invalidate TLB
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mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableCachesAndMmu)
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mrc p15, 0, r0, c1, c0, 0 @ Get control register
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bic r0, r0, #CTRL_M_BIT @ Disable MMU
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bic r0, r0, #CTRL_C_BIT @ Disable D Cache
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bic r0, r0, #CTRL_I_BIT @ Disable I Cache
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mcr p15, 0, r0, c1, c0, 0 @ Write control register
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dsb
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isb
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bx LR
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ASM_FUNC(ArmMmuEnabled)
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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bx LR
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ASM_FUNC(ArmEnableDataCache)
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableDataCache)
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear C bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableInstructionCache)
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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orr R0,R0,R1 @Set I bit
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableInstructionCache)
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 @Read control register configuration data
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bic R0,R0,R1 @Clear I bit.
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mcr p15,0,r0,c1,c0,0 @Write control register configuration data
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dsb
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isb
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bx LR
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ASM_FUNC(ArmEnableSWPInstruction)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000400
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mcr p15, 0, r0, c1, c0, 0
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isb
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bx LR
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ASM_FUNC(ArmEnableBranchPrediction)
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmDisableBranchPrediction)
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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bx LR
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ASM_FUNC(ArmSetLowVectors)
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ASM_FUNC(ArmSetHighVectors)
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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orr r0, r0, #0x00002000 @ Set V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx LR
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ASM_FUNC(ArmDataMemoryBarrier)
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dmb
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bx LR
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ASM_FUNC(ArmDataSynchronizationBarrier)
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dsb
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bx LR
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ASM_FUNC(ArmInstructionSynchronizationBarrier)
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isb
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bx LR
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ASM_FUNC(ArmReadVBar)
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# Set the Address of the Vector Table in the VBAR register
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mrc p15, 0, r0, c12, c0, 0
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bx lr
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ASM_FUNC(ArmWriteVBar)
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# Set the Address of the Vector Table in the VBAR register
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mcr p15, 0, r0, c12, c0, 0
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# Ensure the SCTLR.V bit is clear
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
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bic r0, r0, #0x00002000 @ clear V bit
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mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
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isb
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bx lr
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ASM_FUNC(ArmEnableVFP)
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# Read CPACR (Coprocessor Access Control Register)
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mrc p15, 0, r0, c1, c0, 2
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# Enable VPF access (Full Access to CP10, CP11) (V* instructions)
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orr r0, r0, #0x00f00000
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# Write back CPACR (Coprocessor Access Control Register)
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mcr p15, 0, r0, c1, c0, 2
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isb
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# Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
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mov r0, #0x40000000
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#ifndef __clang__
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mcr p10,#0x7,r0,c8,c0,#0
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#else
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# Set the FPU model so Clang does not choke on the next instruction
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.fpu neon
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vmsr fpexc, r0
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#endif
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bx lr
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ASM_FUNC(ArmCallWFI)
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wfi
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bx lr
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#Note: Return 0 in Uniprocessor implementation
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ASM_FUNC(ArmReadCbar)
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mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
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bx lr
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ASM_FUNC(ArmReadMpidr)
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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bx lr
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ASM_FUNC(ArmReadTpidrurw)
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mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
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bx lr
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ASM_FUNC(ArmWriteTpidrurw)
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mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
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bx lr
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ASM_FUNC(ArmIsArchTimerImplemented)
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mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
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and r0, r0, #0x000F0000
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bx lr
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ASM_FUNC(ArmReadIdPfr1)
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mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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