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cb87aada97
Unlike CPACR_EL1 whose reserved bits are solely RES0, CPTR_EL2 has some RES1 bits, and so we should not clear them unless we know what they mean. For example, when SVE was introduced, CPACR_EL1.ZEN occupied a RES0 field and thus 0 means trap (which is what we get at EL1), but CPTR_EL2.TZ occupied a RES1 field and thus 1 means trap, but we set it to 0, so the environment is inconsistent between EDK2 and EL1 and EL2. Another concrete case is for Morello, where the CEN/TC fields similarly gate access to capability register state, but also alter exception delivery and return, such that VBAR_ELx and ELR_ELx become capabilities. So long as software adheres to RES0/1 this is backwards-compatible, but since EDK2 does not do so here it inadvertently enables capability-based exception delivery and return and thus, when run at EL2, gets stuck in a trap loop when taking its first interrupt, but works just fine at EL1. Fix this by setting all the RES1 fields in CPTR_EL2, following the pattern for CPACR_EL1's non-zero initial value (due to setting FPEN so as to not trap on SIMD/FP use), tested by running ArmVirtQemu-AARCH64 (DEBUG) on Morello QEMU with EL2 enabled. Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
46 lines
1.6 KiB
ArmAsm
46 lines
1.6 KiB
ArmAsm
#========================================================================================
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# Copyright (c) 2011-2017, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#=======================================================================================
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#include <AsmMacroLib.h>
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#include <AArch64/AArch64.h>
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// Setup EL1 while in EL1
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ASM_FUNC(SetupExceptionLevel1)
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mov x5, x30 // Save LR
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mov x0, #CPACR_DEFAULT
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bl ASM_PFX(ArmWriteCpacr) // Enable architectural features
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ret x5
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// Setup EL2 while in EL2
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ASM_FUNC(SetupExceptionLevel2)
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msr sctlr_el2, xzr
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mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
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// Send all interrupts to their respective Exception levels for EL2
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orr x0, x0, #(1 << 3) // Enable EL2 FIQ
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orr x0, x0, #(1 << 4) // Enable EL2 IRQ
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orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
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msr hcr_el2, x0 // Write back our settings
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// NB: We assume that we have not been entered on VHE systems with
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// HCR_EL2.E2H set.
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mov x0, #AARCH64_CPTR_DEFAULT
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msr cptr_el2, x0 // Enable architectural features
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// Enable Timer access for non-secure EL1 and EL0
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// The cnthctl_el2 register bits are architecturally
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// UNKNOWN on reset.
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// Disable event stream as it is not in use at this stage
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mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
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msr cnthctl_el2, x0
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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